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6f024978e7
On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in56b60b8bce("ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller") the second suspend to RAM failed. First suspend worked fine but the next one hang just after powering down of secondary CPUs (system consumed energy as it would be running but was not responsive). The issue was caused by enabling delayed reset assertion for CPU0 just after issuing power down of cores. This was introduced for Exynos4 in13cfa6c4f7("ARM: EXYNOS: Fix CPU idle clock down after CPU off"). The whole behavior is not well documented but after checking with vendor code this should be done like this (on Exynos4): 1. Enable delayed reset assertion when system is running (for all CPUs). 2. Disable delayed reset assertion before suspending the system. This can be done after powering off secondary CPUs. 3. Re-enable the delayed reset assertion when system is resumed. Fixes:13cfa6c4f7("ARM: EXYNOS: Fix CPU idle clock down after CPU off") Cc: <stable@vger.kernel.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
179 lines
4.9 KiB
C
179 lines
4.9 KiB
C
/*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Common Header for EXYNOS machines
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
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#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
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#include <linux/of.h>
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#include <linux/platform_data/cpuidle-exynos.h>
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#define EXYNOS3250_SOC_ID 0xE3472000
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#define EXYNOS3_SOC_MASK 0xFFFFF000
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#define EXYNOS4210_CPU_ID 0x43210000
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#define EXYNOS4212_CPU_ID 0x43220000
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#define EXYNOS4412_CPU_ID 0xE4412200
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#define EXYNOS4_CPU_MASK 0xFFFE0000
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#define EXYNOS5250_SOC_ID 0x43520000
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#define EXYNOS5410_SOC_ID 0xE5410000
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#define EXYNOS5420_SOC_ID 0xE5420000
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#define EXYNOS5440_SOC_ID 0xE5440000
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#define EXYNOS5800_SOC_ID 0xE5422000
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#define EXYNOS5_SOC_MASK 0xFFFFF000
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extern unsigned long samsung_cpu_id;
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#define IS_SAMSUNG_CPU(name, id, mask) \
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static inline int is_samsung_##name(void) \
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{ \
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return ((samsung_cpu_id & mask) == (id & mask)); \
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}
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IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
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IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
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IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
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IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
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IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
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IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
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IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
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IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
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IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
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#if defined(CONFIG_SOC_EXYNOS3250)
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# define soc_is_exynos3250() is_samsung_exynos3250()
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#else
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# define soc_is_exynos3250() 0
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#endif
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#if defined(CONFIG_CPU_EXYNOS4210)
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# define soc_is_exynos4210() is_samsung_exynos4210()
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#else
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# define soc_is_exynos4210() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS4212)
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# define soc_is_exynos4212() is_samsung_exynos4212()
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#else
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# define soc_is_exynos4212() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS4412)
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# define soc_is_exynos4412() is_samsung_exynos4412()
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#else
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# define soc_is_exynos4412() 0
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#endif
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#define EXYNOS4210_REV_0 (0x0)
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#define EXYNOS4210_REV_1_0 (0x10)
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#define EXYNOS4210_REV_1_1 (0x11)
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#if defined(CONFIG_SOC_EXYNOS5250)
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# define soc_is_exynos5250() is_samsung_exynos5250()
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#else
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# define soc_is_exynos5250() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS5410)
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# define soc_is_exynos5410() is_samsung_exynos5410()
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#else
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# define soc_is_exynos5410() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS5420)
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# define soc_is_exynos5420() is_samsung_exynos5420()
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#else
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# define soc_is_exynos5420() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS5440)
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# define soc_is_exynos5440() is_samsung_exynos5440()
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#else
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# define soc_is_exynos5440() 0
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#endif
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#if defined(CONFIG_SOC_EXYNOS5800)
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# define soc_is_exynos5800() is_samsung_exynos5800()
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#else
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# define soc_is_exynos5800() 0
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#endif
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#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
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soc_is_exynos4412())
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#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
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soc_is_exynos5420() || soc_is_exynos5800())
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extern u32 cp15_save_diag;
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extern u32 cp15_save_power;
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extern void __iomem *sysram_ns_base_addr;
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extern void __iomem *sysram_base_addr;
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extern void __iomem *pmu_base_addr;
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void exynos_sysram_init(void);
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enum {
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FW_DO_IDLE_SLEEP,
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FW_DO_IDLE_AFTR,
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};
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void exynos_firmware_init(void);
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/* CPU BOOT mode flag for Exynos3250 SoC bootloader */
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#define C2_STATE (1 << 3)
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void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
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void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
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extern u32 exynos_get_eint_wake_mask(void);
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#ifdef CONFIG_PM_SLEEP
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extern void __init exynos_pm_init(void);
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#else
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static inline void exynos_pm_init(void) {}
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#endif
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extern void exynos_cpu_resume(void);
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extern void exynos_cpu_resume_ns(void);
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extern struct smp_operations exynos_smp_ops;
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extern void exynos_cpu_power_down(int cpu);
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extern void exynos_cpu_power_up(int cpu);
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extern int exynos_cpu_power_state(int cpu);
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extern void exynos_cluster_power_down(int cluster);
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extern void exynos_cluster_power_up(int cluster);
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extern int exynos_cluster_power_state(int cluster);
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extern void exynos_cpu_save_register(void);
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extern void exynos_cpu_restore_register(void);
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extern void exynos_pm_central_suspend(void);
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extern int exynos_pm_central_resume(void);
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extern void exynos_enter_aftr(void);
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extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
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extern void exynos_set_delayed_reset_assertion(bool enable);
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extern void s5p_init_cpu(void __iomem *cpuid_addr);
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extern unsigned int samsung_rev(void);
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extern void __iomem *cpu_boot_reg_base(void);
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static inline void pmu_raw_writel(u32 val, u32 offset)
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{
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__raw_writel(val, pmu_base_addr + offset);
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}
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static inline u32 pmu_raw_readl(u32 offset)
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{
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return __raw_readl(pmu_base_addr + offset);
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}
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#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
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