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linux/arch/x86/kernel/cpu/resctrl
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Reinette Chatre 0c4d5ba1b9 x86/resctrl: Support wider MBM counters 
The original Memory Bandwidth Monitoring (MBM) architectural
definition defines counters of up to 62 bits in the
IA32_QM_CTR MSR while the first-generation MBM implementation
uses statically defined 24 bit counters.

The MBM CPUID enumeration properties have been expanded to include
the MBM counter width, encoded as an offset from 24 bits.

While eight bits are available for the counter width offset IA32_QM_CTR
MSR only supports 62 bit counters. Add a sanity check, with warning
printed when encountered, to ensure counters cannot exceed the 62 bit
limit.

Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/69d52abd5b14794d3a0f05ba7c755ed1f4c0d5ed.1588715690.git.reinette.chatre@intel.com
2020-05-06 18:08:32 +02:00
..
core.c x86/resctrl: Support CPUID enumeration of MBM counter width 2020-05-06 18:02:41 +02:00
ctrlmondata.c x86/resctrl: Maintain MBM counter width per resource 2020-05-06 18:00:35 +02:00
internal.h x86/resctrl: Support wider MBM counters 2020-05-06 18:08:32 +02:00
Makefile x86/resctrl: Avoid confusion over the new X86_RESCTRL config 2019-02-02 10:34:52 +01:00
monitor.c x86/resctrl: Support wider MBM counters 2020-05-06 18:08:32 +02:00
pseudo_lock.c x86/resctrl: Rename asm/resctrl_sched.h to asm/resctrl.h 2020-05-06 17:45:22 +02:00
pseudo_lock_event.h
rdtgroup.c x86/resctrl: Maintain MBM counter width per resource 2020-05-06 18:00:35 +02:00