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https://github.com/torvalds/linux
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1db2a6e1e2
Opportunistically initialize IA32_FEAT_CTL to enable VMX when the MSR is left unlocked by BIOS. Configuring feature control at boot time paves the way for similar enabling of other features, e.g. Software Guard Extensions (SGX). Temporarily leave equivalent KVM code in place in order to avoid introducing a regression on Centaur and Zhaoxin CPUs, e.g. removing KVM's code would leave the MSR unlocked on those CPUs and would break existing functionality if people are loading kvm_intel on Centaur and/or Zhaoxin. Defer enablement of the boot-time configuration on Centaur and Zhaoxin to future patches to aid bisection. Note, Local Machine Check Exceptions (LMCE) are also supported by the kernel and enabled via feature control, but the kernel currently uses LMCE if and only if the feature is explicitly enabled by BIOS. Keep the current behavior to avoid introducing bugs, future patches can opt in to opportunistic enabling if it's deemed desirable to do so. Always lock IA32_FEAT_CTL if it exists, even if the CPU doesn't support VMX, so that other existing and future kernel code that queries the MSR can assume it's locked. Start from a clean slate when constructing the value to write to IA32_FEAT_CTL, i.e. ignore whatever value BIOS left in the MSR so as not to enable random features or fault on the WRMSR. Suggested-by: Borislav Petkov <bp@suse.de> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20191221044513.21680-5-sean.j.christopherson@intel.com
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ARCH_X86_CPU_H
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#define ARCH_X86_CPU_H
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/* attempt to consolidate cpu attributes */
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struct cpu_dev {
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const char *c_vendor;
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/* some have two possibilities for cpuid string */
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const char *c_ident[2];
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void (*c_early_init)(struct cpuinfo_x86 *);
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void (*c_bsp_init)(struct cpuinfo_x86 *);
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void (*c_init)(struct cpuinfo_x86 *);
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void (*c_identify)(struct cpuinfo_x86 *);
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void (*c_detect_tlb)(struct cpuinfo_x86 *);
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int c_x86_vendor;
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#ifdef CONFIG_X86_32
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/* Optional vendor specific routine to obtain the cache size. */
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unsigned int (*legacy_cache_size)(struct cpuinfo_x86 *,
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unsigned int);
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/* Family/stepping-based lookup table for model names. */
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struct legacy_cpu_model_info {
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int family;
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const char *model_names[16];
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} legacy_models[5];
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#endif
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};
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struct _tlb_table {
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unsigned char descriptor;
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char tlb_type;
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unsigned int entries;
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/* unsigned int ways; */
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char info[128];
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};
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#define cpu_dev_register(cpu_devX) \
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static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
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__attribute__((__section__(".x86_cpu_dev.init"))) = \
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&cpu_devX;
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extern const struct cpu_dev *const __x86_cpu_dev_start[],
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*const __x86_cpu_dev_end[];
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#ifdef CONFIG_CPU_SUP_INTEL
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enum tsx_ctrl_states {
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TSX_CTRL_ENABLE,
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TSX_CTRL_DISABLE,
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TSX_CTRL_NOT_SUPPORTED,
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};
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extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
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extern void __init tsx_init(void);
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extern void tsx_enable(void);
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extern void tsx_disable(void);
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#else
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static inline void tsx_init(void) { }
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#endif /* CONFIG_CPU_SUP_INTEL */
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extern void get_cpu_cap(struct cpuinfo_x86 *c);
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extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
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extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
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extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
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extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
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extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
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extern void detect_num_cpu_cores(struct cpuinfo_x86 *c);
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extern int detect_extended_topology_early(struct cpuinfo_x86 *c);
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extern int detect_extended_topology(struct cpuinfo_x86 *c);
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extern int detect_ht_early(struct cpuinfo_x86 *c);
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extern void detect_ht(struct cpuinfo_x86 *c);
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unsigned int aperfmperf_get_khz(int cpu);
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extern void x86_spec_ctrl_setup_ap(void);
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extern u64 x86_read_arch_cap_msr(void);
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#ifdef CONFIG_IA32_FEAT_CTL
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void init_ia32_feat_ctl(struct cpuinfo_x86 *c);
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#endif
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#endif /* ARCH_X86_CPU_H */
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