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9bb04a0c4e
Add Precision Time Measurement (PTM) support (see PCIe r3.1, sec 6.22). Enable PTM on PTM Root devices and switch ports. This does not enable PTM on endpoints. There currently are no PTM-capable devices on the market, but it is expected to be supported by the Intel Apollo Lake platform. [bhelgaas: complete rework] Signed-off-by: Jonathan Yong <jonathan.yong@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
71 lines
1.8 KiB
C
71 lines
1.8 KiB
C
/*
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* PCI Express Precision Time Measurement
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* Copyright (c) 2016, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include "../pci.h"
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static void pci_ptm_info(struct pci_dev *dev)
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{
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dev_info(&dev->dev, "PTM enabled%s\n", dev->ptm_root ? " (root)" : "");
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}
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void pci_ptm_init(struct pci_dev *dev)
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{
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int pos;
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u32 cap, ctrl;
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struct pci_dev *ups;
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if (!pci_is_pcie(dev))
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return;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
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if (!pos)
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return;
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/*
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* Enable PTM only on interior devices (root ports, switch ports,
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* etc.) on the assumption that it causes no link traffic until an
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* endpoint enables it.
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*/
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if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
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pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
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return;
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pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
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/*
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* There's no point in enabling PTM unless it's enabled in the
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* upstream device or this device can be a PTM Root itself. Per
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* the spec recommendation (PCIe r3.1, sec 7.32.3), select the
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* furthest upstream Time Source as the PTM Root.
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*/
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ups = pci_upstream_bridge(dev);
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if (ups && ups->ptm_enabled) {
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ctrl = PCI_PTM_CTRL_ENABLE;
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} else {
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if (cap & PCI_PTM_CAP_ROOT) {
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ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
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dev->ptm_root = 1;
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} else
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return;
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}
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pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
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dev->ptm_enabled = 1;
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pci_ptm_info(dev);
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}
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