linux/arch/riscv
Alexandre Ghiti 9b79878ced
riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED
Make the physical RAM base address available for all kernels, not only
XIP kernels as it will allow to simplify address conversions macros.

Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-06-11 14:29:12 -07:00
..
boot RISC-V Patches for the 5.13 Merge Window, Part 1 2021-05-06 09:24:18 -07:00
configs RISC-V: Enable Microchip PolarFire ICICLE SoC 2021-04-26 08:31:32 -07:00
errata riscv: sifive: Apply errata "cip-1200" patch 2021-04-26 08:24:58 -07:00
include riscv: Consistify protect_kernel_linear_mapping_text_rodata() use 2021-05-06 09:40:15 -07:00
kernel riscv: remove unused handle_exception symbol 2021-05-06 09:40:16 -07:00
lib riscv: Add support for function error injection 2021-01-14 15:09:09 -08:00
mm riscv: mm: Fix W+X mappings at boot 2021-06-01 21:15:09 -07:00
net riscv: bpf: Avoid breaking W^X 2021-04-26 08:25:14 -07:00
Kbuild riscv: Allow device trees to be built into the kernel 2020-05-18 11:38:05 -07:00
Kconfig riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED 2021-06-11 14:29:12 -07:00
Kconfig.debug
Kconfig.erratas riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y 2021-05-06 09:40:13 -07:00
Kconfig.socs RISC-V Patches for the 5.13 Merge Window, Part 1 2021-05-06 09:24:18 -07:00
Makefile RISC-V: enable XIP 2021-04-26 08:31:28 -07:00