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99312c377f
The clock generation does not match reality when using the CAN IP core outside of the FPGA design. This patch fixes the computation of values which are programmed into the clock generator registers. First, there are some off-by-one errors which manifest themselves only when communicating with different controller, so those are fixed. Second, the bits in the clock generator registers have different meaning depending on whether the core is in ISO CANFD mode or any of the other modes (BOSCH CANFD or CAN2.0). Detect the ISO CANFD mode and fix handling of this special case of clock configuration. Finally, the CAN clock speed is in CANCLOCK register, not SYSCLOCK register, so fix this as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marc Kleine-Budde <mkl@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Oliver Hartkopp <socketcan@hartkopp.net> Cc: Wolfgang Grandegger <wg@grandegger.com> Reviewed-by: Oliver Hartkopp <socketcan@hartkopp.net> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> |
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| .. | ||
| c_can | ||
| cc770 | ||
| ifi_canfd | ||
| m_can | ||
| mscan | ||
| sja1000 | ||
| softing | ||
| spi | ||
| usb | ||
| at91_can.c | ||
| bfin_can.c | ||
| dev.c | ||
| flexcan.c | ||
| grcan.c | ||
| janz-ican3.c | ||
| Kconfig | ||
| led.c | ||
| Makefile | ||
| pch_can.c | ||
| rcar_can.c | ||
| slcan.c | ||
| sun4i_can.c | ||
| ti_hecc.c | ||
| vcan.c | ||
| xilinx_can.c | ||