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https://github.com/torvalds/linux
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146 lines
4 KiB
C
146 lines
4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000, 2001 Keith M Wesolowski
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <asm/ip32/mace.h>
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#include <asm/ip32/ip32_ints.h>
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#undef DEBUG_MACE_PCI
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/*
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* Handle errors from the bridge. This includes master and target aborts,
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* various command and address errors, and the interrupt test. This gets
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* registered on the bridge error irq. It's conceivable that some of these
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* conditions warrant a panic. Anybody care to say which ones?
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*/
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static irqreturn_t macepci_error(int irq, void *dev)
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{
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char s;
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unsigned int flags = mace->pci.error;
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unsigned int addr = mace->pci.error_addr;
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if (flags & MACEPCI_ERROR_MEMORY_ADDR)
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s = 'M';
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else if (flags & MACEPCI_ERROR_CONFIG_ADDR)
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s = 'C';
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else
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s = 'X';
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if (flags & MACEPCI_ERROR_MASTER_ABORT) {
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printk("MACEPCI: Master abort at 0x%08x (%c)\n", addr, s);
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flags &= ~MACEPCI_ERROR_MASTER_ABORT;
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}
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if (flags & MACEPCI_ERROR_TARGET_ABORT) {
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printk("MACEPCI: Target abort at 0x%08x (%c)\n", addr, s);
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flags &= ~MACEPCI_ERROR_TARGET_ABORT;
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}
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if (flags & MACEPCI_ERROR_DATA_PARITY_ERR) {
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printk("MACEPCI: Data parity error at 0x%08x (%c)\n", addr, s);
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flags &= ~MACEPCI_ERROR_DATA_PARITY_ERR;
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}
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if (flags & MACEPCI_ERROR_RETRY_ERR) {
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printk("MACEPCI: Retry error at 0x%08x (%c)\n", addr, s);
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flags &= ~MACEPCI_ERROR_RETRY_ERR;
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}
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if (flags & MACEPCI_ERROR_ILLEGAL_CMD) {
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printk("MACEPCI: Illegal command at 0x%08x (%c)\n", addr, s);
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flags &= ~MACEPCI_ERROR_ILLEGAL_CMD;
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}
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if (flags & MACEPCI_ERROR_SYSTEM_ERR) {
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printk("MACEPCI: System error at 0x%08x (%c)\n", addr, s);
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flags &= ~MACEPCI_ERROR_SYSTEM_ERR;
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}
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if (flags & MACEPCI_ERROR_PARITY_ERR) {
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printk("MACEPCI: Parity error at 0x%08x (%c)\n", addr, s);
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flags &= ~MACEPCI_ERROR_PARITY_ERR;
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}
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if (flags & MACEPCI_ERROR_OVERRUN) {
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printk("MACEPCI: Overrun error at 0x%08x (%c)\n", addr, s);
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flags &= ~MACEPCI_ERROR_OVERRUN;
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}
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if (flags & MACEPCI_ERROR_SIG_TABORT) {
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printk("MACEPCI: Signaled target abort (clearing)\n");
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flags &= ~MACEPCI_ERROR_SIG_TABORT;
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}
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if (flags & MACEPCI_ERROR_INTERRUPT_TEST) {
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printk("MACEPCI: Interrupt test triggered (clearing)\n");
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flags &= ~MACEPCI_ERROR_INTERRUPT_TEST;
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}
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mace->pci.error = flags;
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return IRQ_HANDLED;
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}
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extern struct pci_ops mace_pci_ops;
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#ifdef CONFIG_64BIT
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static struct resource mace_pci_mem_resource = {
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.name = "SGI O2 PCI MEM",
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.start = MACEPCI_HI_MEMORY,
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.end = 0x2FFFFFFFFUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource mace_pci_io_resource = {
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.name = "SGI O2 PCI IO",
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.start = 0x00000000UL,
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.end = 0xffffffffUL,
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.flags = IORESOURCE_IO,
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};
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#define MACE_PCI_MEM_OFFSET 0x200000000
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#else
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static struct resource mace_pci_mem_resource = {
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.name = "SGI O2 PCI MEM",
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.start = MACEPCI_LOW_MEMORY,
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.end = MACEPCI_LOW_MEMORY + 0x2000000 - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource mace_pci_io_resource = {
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.name = "SGI O2 PCI IO",
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.start = 0x00000000,
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.end = 0xFFFFFFFF,
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.flags = IORESOURCE_IO,
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};
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#define MACE_PCI_MEM_OFFSET (MACEPCI_LOW_MEMORY - 0x80000000)
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#endif
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static struct pci_controller mace_pci_controller = {
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.pci_ops = &mace_pci_ops,
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.mem_resource = &mace_pci_mem_resource,
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.io_resource = &mace_pci_io_resource,
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.iommu = 0,
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.mem_offset = MACE_PCI_MEM_OFFSET,
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.io_offset = 0,
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};
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static int __init mace_init(void)
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{
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PCIBIOS_MIN_IO = 0x1000;
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/* Clear any outstanding errors and enable interrupts */
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mace->pci.error_addr = 0;
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mace->pci.error = 0;
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mace->pci.control = 0xff008500;
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printk("MACE PCI rev %d\n", mace->pci.rev);
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BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
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"MACE PCI error", NULL));
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iomem_resource = mace_pci_mem_resource;
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ioport_resource = mace_pci_io_resource;
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register_pci_controller(&mace_pci_controller);
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return 0;
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}
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arch_initcall(mace_init);
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