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7f613c7d22
The bulk of the change. Use per cpu MCA/INIT stacks. Change the SAL to OS state (sos) to be per process. Do all the assembler work on the MCA/INIT stacks, leaving the original stack alone. Pass per cpu state data to the C handlers for MCA and INIT, which also means changing the mca_drv interfaces slightly. Lots of verification on whether the original stack is usable before converting it to a sleeping process. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
241 lines
7.1 KiB
C
241 lines
7.1 KiB
C
/*
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* File: mca_asm.h
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*
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) Vijay Chander (vijay@engr.sgi.com)
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* Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
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* Copyright (C) 2000 Hewlett-Packard Co.
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* Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 2002 Intel Corp.
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* Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
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* Copyright (C) 2005 Silicon Graphics, Inc
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* Copyright (C) 2005 Keith Owens <kaos@sgi.com>
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*/
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#ifndef _ASM_IA64_MCA_ASM_H
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#define _ASM_IA64_MCA_ASM_H
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#define PSR_IC 13
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#define PSR_I 14
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#define PSR_DT 17
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#define PSR_RT 27
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#define PSR_MC 35
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#define PSR_IT 36
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#define PSR_BN 44
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/*
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* This macro converts a instruction virtual address to a physical address
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* Right now for simulation purposes the virtual addresses are
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* direct mapped to physical addresses.
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* 1. Lop off bits 61 thru 63 in the virtual address
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*/
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#define INST_VA_TO_PA(addr) \
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dep addr = 0, addr, 61, 3
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/*
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* This macro converts a data virtual address to a physical address
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* Right now for simulation purposes the virtual addresses are
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* direct mapped to physical addresses.
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* 1. Lop off bits 61 thru 63 in the virtual address
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*/
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#define DATA_VA_TO_PA(addr) \
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tpa addr = addr
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/*
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* This macro converts a data physical address to a virtual address
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* Right now for simulation purposes the virtual addresses are
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* direct mapped to physical addresses.
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* 1. Put 0x7 in bits 61 thru 63.
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*/
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#define DATA_PA_TO_VA(addr,temp) \
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mov temp = 0x7 ;; \
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dep addr = temp, addr, 61, 3
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#define GET_THIS_PADDR(reg, var) \
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mov reg = IA64_KR(PER_CPU_DATA);; \
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addl reg = THIS_CPU(var), reg
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/*
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* This macro jumps to the instruction at the given virtual address
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* and starts execution in physical mode with all the address
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* translations turned off.
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* 1. Save the current psr
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* 2. Make sure that all the upper 32 bits are off
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*
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* 3. Clear the interrupt enable and interrupt state collection bits
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* in the psr before updating the ipsr and iip.
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*
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* 4. Turn off the instruction, data and rse translation bits of the psr
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* and store the new value into ipsr
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* Also make sure that the interrupts are disabled.
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* Ensure that we are in little endian mode.
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* [psr.{rt, it, dt, i, be} = 0]
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*
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* 5. Get the physical address corresponding to the virtual address
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* of the next instruction bundle and put it in iip.
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* (Using magic numbers 24 and 40 in the deposint instruction since
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* the IA64_SDK code directly maps to lower 24bits as physical address
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* from a virtual address).
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*
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* 6. Do an rfi to move the values from ipsr to psr and iip to ip.
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*/
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#define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
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mov old_psr = psr; \
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;; \
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dep old_psr = 0, old_psr, 32, 32; \
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\
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mov ar.rsc = 0 ; \
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;; \
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srlz.d; \
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mov temp2 = ar.bspstore; \
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;; \
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DATA_VA_TO_PA(temp2); \
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;; \
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mov temp1 = ar.rnat; \
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;; \
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mov ar.bspstore = temp2; \
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;; \
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mov ar.rnat = temp1; \
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mov temp1 = psr; \
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mov temp2 = psr; \
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;; \
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\
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dep temp2 = 0, temp2, PSR_IC, 2; \
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;; \
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mov psr.l = temp2; \
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;; \
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srlz.d; \
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dep temp1 = 0, temp1, 32, 32; \
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;; \
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dep temp1 = 0, temp1, PSR_IT, 1; \
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;; \
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dep temp1 = 0, temp1, PSR_DT, 1; \
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;; \
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dep temp1 = 0, temp1, PSR_RT, 1; \
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;; \
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dep temp1 = 0, temp1, PSR_I, 1; \
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;; \
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dep temp1 = 0, temp1, PSR_IC, 1; \
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;; \
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dep temp1 = -1, temp1, PSR_MC, 1; \
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;; \
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mov cr.ipsr = temp1; \
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;; \
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LOAD_PHYSICAL(p0, temp2, start_addr); \
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;; \
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mov cr.iip = temp2; \
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mov cr.ifs = r0; \
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DATA_VA_TO_PA(sp); \
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DATA_VA_TO_PA(gp); \
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;; \
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srlz.i; \
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;; \
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nop 1; \
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nop 2; \
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nop 1; \
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nop 2; \
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rfi; \
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;;
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/*
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* This macro jumps to the instruction at the given virtual address
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* and starts execution in virtual mode with all the address
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* translations turned on.
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* 1. Get the old saved psr
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*
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* 2. Clear the interrupt state collection bit in the current psr.
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*
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* 3. Set the instruction translation bit back in the old psr
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* Note we have to do this since we are right now saving only the
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* lower 32-bits of old psr.(Also the old psr has the data and
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* rse translation bits on)
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*
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* 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1.
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*
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* 5. Reset the current thread pointer (r13).
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*
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* 6. Set iip to the virtual address of the next instruction bundle.
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*
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* 7. Do an rfi to move ipsr to psr and iip to ip.
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*/
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#define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
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mov temp2 = psr; \
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;; \
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mov old_psr = temp2; \
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;; \
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dep temp2 = 0, temp2, PSR_IC, 2; \
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;; \
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mov psr.l = temp2; \
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mov ar.rsc = 0; \
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;; \
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srlz.d; \
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mov r13 = ar.k6; \
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mov temp2 = ar.bspstore; \
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;; \
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DATA_PA_TO_VA(temp2,temp1); \
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;; \
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mov temp1 = ar.rnat; \
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;; \
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mov ar.bspstore = temp2; \
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;; \
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mov ar.rnat = temp1; \
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;; \
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mov temp1 = old_psr; \
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;; \
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mov temp2 = 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_IC, 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_IT, 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_DT, 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_RT, 1; \
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;; \
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dep temp1 = temp2, temp1, PSR_BN, 1; \
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;; \
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\
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mov cr.ipsr = temp1; \
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movl temp2 = start_addr; \
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;; \
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mov cr.iip = temp2; \
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;; \
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DATA_PA_TO_VA(sp, temp1); \
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DATA_PA_TO_VA(gp, temp2); \
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srlz.i; \
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;; \
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nop 1; \
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nop 2; \
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nop 1; \
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rfi \
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;;
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/*
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* The MCA and INIT stacks in struct ia64_mca_cpu look like normal kernel
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* stacks, except that the SAL/OS state and a switch_stack are stored near the
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* top of the MCA/INIT stack. To support concurrent entry to MCA or INIT, as
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* well as MCA over INIT, each event needs its own SAL/OS state. All entries
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* are 16 byte aligned.
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*
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* +---------------------------+
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* | pt_regs |
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* +---------------------------+
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* | switch_stack |
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* +---------------------------+
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* | SAL/OS state |
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* +---------------------------+
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* | 16 byte scratch area |
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* +---------------------------+ <-------- SP at start of C MCA handler
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* | ..... |
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* +---------------------------+
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* | RBS for MCA/INIT handler |
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* +---------------------------+
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* | struct task for MCA/INIT |
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* +---------------------------+ <-------- Bottom of MCA/INIT stack
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*/
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#define ALIGN16(x) ((x)&~15)
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#define MCA_PT_REGS_OFFSET ALIGN16(KERNEL_STACK_SIZE-IA64_PT_REGS_SIZE)
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#define MCA_SWITCH_STACK_OFFSET ALIGN16(MCA_PT_REGS_OFFSET-IA64_SWITCH_STACK_SIZE)
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#define MCA_SOS_OFFSET ALIGN16(MCA_SWITCH_STACK_OFFSET-IA64_SAL_OS_STATE_SIZE)
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#define MCA_SP_OFFSET ALIGN16(MCA_SOS_OFFSET-16)
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#endif /* _ASM_IA64_MCA_ASM_H */
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