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984ca29501
Add IRQC interrupt controller support to r8a73a4 by hooking up two IRQC instances to handle 58 external IRQ signals. There IRQC controllers are tied to SPIs of the GIC. On r8a73a4 exact IRQ pin routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
88 lines
2.1 KiB
Plaintext
88 lines
2.1 KiB
Plaintext
/*
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* Device Tree Source for the r8a73a4 SoC
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "renesas,r8a73a4";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1500000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xf1001000 0x1000>,
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<0xf1002000 0x1000>,
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<0xf1004000 0x2000>,
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<0xf1006000 0x2000>;
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interrupts = <1 9 0xf04>;
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gic-cpuif@4 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <4>;
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cpu = <&cpu0>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe61c0000 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
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<0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
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<0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
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<0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
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<0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
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<0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
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<0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
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<0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
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};
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irqc1: interrupt-controller@e61c0200 {
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compatible = "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe61c0200 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
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<0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
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<0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
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<0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
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<0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
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<0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
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<0 56 4>, <0 57 4>;
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};
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};
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