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33419a69a5
When booting secondary CPUs we have used the main CPU to set up the Snoop Control Unit flags of these CPUs. It is a cleaner approach if every CPU takes care of its own flags. We avoid the need for locking and the program logic is more concise. With this patch the file headsmp-sh73a0.S is added that contains a startup vector for secondary CPUs that sets up its own SCU flags. Further in sh73a0_smp_prepare_cpus() we can rely on the generic ARM helper scu_power_mode(). This is possible as we don't cross borders anymore (every CPU handles its own flags) and need no locking. So we can throw out the needless function modify_scu_cpu_psr(). Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
51 lines
1.7 KiB
ArmAsm
51 lines
1.7 KiB
ArmAsm
/*
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* SMP support for SoC sh73a0
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*
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* Copyright (C) 2012 Bastian Hecht
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/memory.h>
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__CPUINIT
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/*
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* Reset vector for secondary CPUs.
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*
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* First we turn on L1 cache coherency for our CPU. Then we jump to
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* shmobile_invalidate_start that invalidates the cache and hands over control
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* to the common ARM startup code.
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* This function will be mapped to address 0 by the SBAR register.
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* A normal branch is out of range here so we need a long jump. We jump to
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* the physical address as the MMU is still turned off.
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*/
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.align 12
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ENTRY(sh73a0_secondary_vector)
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mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
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and r0, r0, #3 @ mask out cpu ID
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lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
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mov r1, #0xf0000000 @ SCU base address
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ldr r2, [r1, #8] @ SCU Power Status Register
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mov r3, #3
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bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
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str r2, [r1, #8] @ write back
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ldr pc, 1f
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1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
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ENDPROC(sh73a0_secondary_vector)
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