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![Uwe Kleine-König](/assets/img/avatar_default.png)
This prepares the pwm-samsung driver to further changes of the pwm core outlined in the commit introducing devm_pwmchip_alloc(). There is no intended semantical change and the driver should behave as before. Link: https://lore.kernel.org/r/f188e68bdea8d5a24277a10c8c9a6350a9c246ac.1707900770.git.u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
650 lines
17 KiB
C
650 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2007 Ben Dooks
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* Copyright (c) 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
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* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
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* Copyright (c) 2017 Samsung Electronics Co., Ltd.
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*
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* PWM driver for Samsung SoCs
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/export.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/time.h>
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/* For struct samsung_timer_variant and samsung_pwm_lock. */
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#include <clocksource/samsung_pwm.h>
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#define REG_TCFG0 0x00
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#define REG_TCFG1 0x04
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#define REG_TCON 0x08
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#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
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#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
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#define TCFG0_PRESCALER_MASK 0xff
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#define TCFG0_PRESCALER1_SHIFT 8
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#define TCFG1_MUX_MASK 0xf
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#define TCFG1_SHIFT(chan) (4 * (chan))
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/*
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* Each channel occupies 4 bits in TCON register, but there is a gap of 4
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* bits (one channel) after channel 0, so channels have different numbering
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* when accessing TCON register. See to_tcon_channel() function.
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*
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* In addition, the location of autoreload bit for channel 4 (TCON channel 5)
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* in its set of bits is 2 as opposed to 3 for other channels.
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*/
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#define TCON_START(chan) BIT(4 * (chan) + 0)
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#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
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#define TCON_INVERT(chan) BIT(4 * (chan) + 2)
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#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
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#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
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#define TCON_AUTORELOAD(chan) \
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((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
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/**
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* struct samsung_pwm_channel - private data of PWM channel
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* @period_ns: current period in nanoseconds programmed to the hardware
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* @duty_ns: current duty time in nanoseconds programmed to the hardware
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* @tin_ns: time of one timer tick in nanoseconds with current timer rate
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*/
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struct samsung_pwm_channel {
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u32 period_ns;
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u32 duty_ns;
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u32 tin_ns;
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};
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/**
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* struct samsung_pwm_chip - private data of PWM chip
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* @variant: local copy of hardware variant data
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* @inverter_mask: inverter status for all channels - one bit per channel
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* @disabled_mask: disabled status for all channels - one bit per channel
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* @base: base address of mapped PWM registers
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* @base_clk: base clock used to drive the timers
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* @tclk0: external clock 0 (can be ERR_PTR if not present)
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* @tclk1: external clock 1 (can be ERR_PTR if not present)
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* @channel: per channel driver data
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*/
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struct samsung_pwm_chip {
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struct samsung_pwm_variant variant;
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u8 inverter_mask;
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u8 disabled_mask;
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void __iomem *base;
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struct clk *base_clk;
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struct clk *tclk0;
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struct clk *tclk1;
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struct samsung_pwm_channel channel[SAMSUNG_PWM_NUM];
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};
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#ifndef CONFIG_CLKSRC_SAMSUNG_PWM
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/*
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* PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
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* and some registers need access synchronization. If both drivers are
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* compiled in, the spinlock is defined in the clocksource driver,
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* otherwise following definition is used.
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*
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* Currently we do not need any more complex synchronization method
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* because all the supported SoCs contain only one instance of the PWM
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* IP. Should this change, both drivers will need to be modified to
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* properly synchronize accesses to particular instances.
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*/
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static DEFINE_SPINLOCK(samsung_pwm_lock);
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#endif
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static inline
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struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
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{
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return pwmchip_get_drvdata(chip);
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}
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static inline unsigned int to_tcon_channel(unsigned int channel)
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{
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/* TCON register has a gap of 4 bits (1 channel) after channel 0 */
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return (channel == 0) ? 0 : (channel + 1);
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}
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static void __pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip,
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struct pwm_device *pwm)
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{
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unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
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u32 tcon;
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tcon = readl(our_chip->base + REG_TCON);
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tcon |= TCON_MANUALUPDATE(tcon_chan);
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writel(tcon, our_chip->base + REG_TCON);
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tcon &= ~TCON_MANUALUPDATE(tcon_chan);
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writel(tcon, our_chip->base + REG_TCON);
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}
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static void pwm_samsung_set_divisor(struct samsung_pwm_chip *our_chip,
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unsigned int channel, u8 divisor)
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{
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u8 shift = TCFG1_SHIFT(channel);
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unsigned long flags;
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u32 reg;
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u8 bits;
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bits = (fls(divisor) - 1) - our_chip->variant.div_base;
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spin_lock_irqsave(&samsung_pwm_lock, flags);
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reg = readl(our_chip->base + REG_TCFG1);
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reg &= ~(TCFG1_MUX_MASK << shift);
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reg |= bits << shift;
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writel(reg, our_chip->base + REG_TCFG1);
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spin_unlock_irqrestore(&samsung_pwm_lock, flags);
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}
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static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *our_chip, unsigned int chan)
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{
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struct samsung_pwm_variant *variant = &our_chip->variant;
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u32 reg;
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reg = readl(our_chip->base + REG_TCFG1);
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reg >>= TCFG1_SHIFT(chan);
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reg &= TCFG1_MUX_MASK;
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return (BIT(reg) & variant->tclk_mask) == 0;
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}
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static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *our_chip,
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unsigned int chan)
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{
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unsigned long rate;
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u32 reg;
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rate = clk_get_rate(our_chip->base_clk);
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reg = readl(our_chip->base + REG_TCFG0);
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if (chan >= 2)
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reg >>= TCFG0_PRESCALER1_SHIFT;
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reg &= TCFG0_PRESCALER_MASK;
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return rate / (reg + 1);
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}
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static unsigned long pwm_samsung_calc_tin(struct pwm_chip *chip,
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unsigned int chan, unsigned long freq)
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{
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
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struct samsung_pwm_variant *variant = &our_chip->variant;
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unsigned long rate;
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struct clk *clk;
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u8 div;
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if (!pwm_samsung_is_tdiv(our_chip, chan)) {
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clk = (chan < 2) ? our_chip->tclk0 : our_chip->tclk1;
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if (!IS_ERR(clk)) {
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rate = clk_get_rate(clk);
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if (rate)
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return rate;
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}
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dev_warn(pwmchip_parent(chip),
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"tclk of PWM %d is inoperational, using tdiv\n", chan);
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}
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rate = pwm_samsung_get_tin_rate(our_chip, chan);
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dev_dbg(pwmchip_parent(chip), "tin parent at %lu\n", rate);
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/*
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* Compare minimum PWM frequency that can be achieved with possible
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* divider settings and choose the lowest divisor that can generate
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* frequencies lower than requested.
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*/
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if (variant->bits < 32) {
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/* Only for s3c24xx */
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for (div = variant->div_base; div < 4; ++div)
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if ((rate >> (variant->bits + div)) < freq)
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break;
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} else {
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/*
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* Other variants have enough counter bits to generate any
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* requested rate, so no need to check higher divisors.
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*/
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div = variant->div_base;
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}
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pwm_samsung_set_divisor(our_chip, chan, BIT(div));
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return rate >> div;
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}
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static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
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if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
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dev_warn(pwmchip_parent(chip),
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"tried to request PWM channel %d without output\n",
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pwm->hwpwm);
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return -EINVAL;
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}
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memset(&our_chip->channel[pwm->hwpwm], 0, sizeof(our_chip->channel[pwm->hwpwm]));
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return 0;
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}
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static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
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unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
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unsigned long flags;
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u32 tcon;
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spin_lock_irqsave(&samsung_pwm_lock, flags);
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tcon = readl(our_chip->base + REG_TCON);
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tcon &= ~TCON_START(tcon_chan);
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tcon |= TCON_MANUALUPDATE(tcon_chan);
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writel(tcon, our_chip->base + REG_TCON);
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tcon &= ~TCON_MANUALUPDATE(tcon_chan);
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tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
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writel(tcon, our_chip->base + REG_TCON);
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our_chip->disabled_mask &= ~BIT(pwm->hwpwm);
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spin_unlock_irqrestore(&samsung_pwm_lock, flags);
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return 0;
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}
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static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
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unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
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unsigned long flags;
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u32 tcon;
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spin_lock_irqsave(&samsung_pwm_lock, flags);
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tcon = readl(our_chip->base + REG_TCON);
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tcon &= ~TCON_AUTORELOAD(tcon_chan);
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writel(tcon, our_chip->base + REG_TCON);
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/*
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* In case the PWM is at 100% duty cycle, force a manual
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* update to prevent the signal from staying high.
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*/
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if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U)
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__pwm_samsung_manual_update(our_chip, pwm);
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our_chip->disabled_mask |= BIT(pwm->hwpwm);
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spin_unlock_irqrestore(&samsung_pwm_lock, flags);
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}
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static void pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip,
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struct pwm_device *pwm)
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{
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unsigned long flags;
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spin_lock_irqsave(&samsung_pwm_lock, flags);
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__pwm_samsung_manual_update(our_chip, pwm);
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spin_unlock_irqrestore(&samsung_pwm_lock, flags);
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}
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static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns, bool force_period)
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{
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
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struct samsung_pwm_channel *chan = &our_chip->channel[pwm->hwpwm];
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u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
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tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
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oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
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/* We need tick count for calculation, not last tick. */
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++tcnt;
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/* Check to see if we are changing the clock rate of the PWM. */
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if (chan->period_ns != period_ns || force_period) {
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unsigned long tin_rate;
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u32 period;
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period = NSEC_PER_SEC / period_ns;
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dev_dbg(pwmchip_parent(chip), "duty_ns=%d, period_ns=%d (%u)\n",
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duty_ns, period_ns, period);
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tin_rate = pwm_samsung_calc_tin(chip, pwm->hwpwm, period);
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dev_dbg(pwmchip_parent(chip), "tin_rate=%lu\n", tin_rate);
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tin_ns = NSEC_PER_SEC / tin_rate;
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tcnt = period_ns / tin_ns;
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}
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/* Period is too short. */
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if (tcnt <= 1)
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return -ERANGE;
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/* Note that counters count down. */
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tcmp = duty_ns / tin_ns;
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/* 0% duty is not available */
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if (!tcmp)
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++tcmp;
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tcmp = tcnt - tcmp;
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/* Decrement to get tick numbers, instead of tick counts. */
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--tcnt;
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/* -1UL will give 100% duty. */
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--tcmp;
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dev_dbg(pwmchip_parent(chip), "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
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/* Update PWM registers. */
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writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
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writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
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/*
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* In case the PWM is currently at 100% duty cycle, force a manual
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* update to prevent the signal staying high if the PWM is disabled
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* shortly afer this update (before it autoreloaded the new values).
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*/
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if (oldtcmp == (u32) -1) {
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dev_dbg(pwmchip_parent(chip), "Forcing manual update");
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pwm_samsung_manual_update(our_chip, pwm);
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}
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chan->period_ns = period_ns;
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chan->tin_ns = tin_ns;
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chan->duty_ns = duty_ns;
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return 0;
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}
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static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false);
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}
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static void pwm_samsung_set_invert(struct samsung_pwm_chip *our_chip,
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unsigned int channel, bool invert)
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{
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unsigned int tcon_chan = to_tcon_channel(channel);
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unsigned long flags;
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u32 tcon;
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spin_lock_irqsave(&samsung_pwm_lock, flags);
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tcon = readl(our_chip->base + REG_TCON);
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if (invert) {
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our_chip->inverter_mask |= BIT(channel);
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tcon |= TCON_INVERT(tcon_chan);
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} else {
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our_chip->inverter_mask &= ~BIT(channel);
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tcon &= ~TCON_INVERT(tcon_chan);
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}
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writel(tcon, our_chip->base + REG_TCON);
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spin_unlock_irqrestore(&samsung_pwm_lock, flags);
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}
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static int pwm_samsung_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
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bool invert = (polarity == PWM_POLARITY_NORMAL);
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/* Inverted means normal in the hardware. */
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pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
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return 0;
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}
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static int pwm_samsung_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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int err, enabled = pwm->state.enabled;
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if (state->polarity != pwm->state.polarity) {
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if (enabled) {
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pwm_samsung_disable(chip, pwm);
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enabled = false;
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}
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err = pwm_samsung_set_polarity(chip, pwm, state->polarity);
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if (err)
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return err;
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}
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if (!state->enabled) {
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if (enabled)
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pwm_samsung_disable(chip, pwm);
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return 0;
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}
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/*
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* We currently avoid using 64bit arithmetic by using the
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* fact that anything faster than 1Hz is easily representable
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* by 32bits.
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*/
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if (state->period > NSEC_PER_SEC)
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return -ERANGE;
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err = pwm_samsung_config(chip, pwm, state->duty_cycle, state->period);
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if (err)
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return err;
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if (!pwm->state.enabled)
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err = pwm_samsung_enable(chip, pwm);
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return err;
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}
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static const struct pwm_ops pwm_samsung_ops = {
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.request = pwm_samsung_request,
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.apply = pwm_samsung_apply,
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};
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#ifdef CONFIG_OF
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static const struct samsung_pwm_variant s3c24xx_variant = {
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.bits = 16,
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.div_base = 1,
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.has_tint_cstat = false,
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.tclk_mask = BIT(4),
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};
|
|
|
|
static const struct samsung_pwm_variant s3c64xx_variant = {
|
|
.bits = 32,
|
|
.div_base = 0,
|
|
.has_tint_cstat = true,
|
|
.tclk_mask = BIT(7) | BIT(6) | BIT(5),
|
|
};
|
|
|
|
static const struct samsung_pwm_variant s5p64x0_variant = {
|
|
.bits = 32,
|
|
.div_base = 0,
|
|
.has_tint_cstat = true,
|
|
.tclk_mask = 0,
|
|
};
|
|
|
|
static const struct samsung_pwm_variant s5pc100_variant = {
|
|
.bits = 32,
|
|
.div_base = 0,
|
|
.has_tint_cstat = true,
|
|
.tclk_mask = BIT(5),
|
|
};
|
|
|
|
static const struct of_device_id samsung_pwm_matches[] = {
|
|
{ .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
|
|
{ .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
|
|
{ .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
|
|
{ .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
|
|
{ .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
|
|
|
|
static int pwm_samsung_parse_dt(struct pwm_chip *chip)
|
|
{
|
|
struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
|
|
struct device_node *np = pwmchip_parent(chip)->of_node;
|
|
const struct of_device_id *match;
|
|
struct property *prop;
|
|
const __be32 *cur;
|
|
u32 val;
|
|
|
|
match = of_match_node(samsung_pwm_matches, np);
|
|
if (!match)
|
|
return -ENODEV;
|
|
|
|
memcpy(&our_chip->variant, match->data, sizeof(our_chip->variant));
|
|
|
|
of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
|
|
if (val >= SAMSUNG_PWM_NUM) {
|
|
dev_err(pwmchip_parent(chip),
|
|
"%s: invalid channel index in samsung,pwm-outputs property\n",
|
|
__func__);
|
|
continue;
|
|
}
|
|
our_chip->variant.output_mask |= BIT(val);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static int pwm_samsung_parse_dt(struct pwm_chip *chip)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
#endif
|
|
|
|
static int pwm_samsung_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct samsung_pwm_chip *our_chip;
|
|
struct pwm_chip *chip;
|
|
unsigned int chan;
|
|
int ret;
|
|
|
|
chip = devm_pwmchip_alloc(&pdev->dev, SAMSUNG_PWM_NUM, sizeof(*our_chip));
|
|
if (IS_ERR(chip))
|
|
return PTR_ERR(chip);
|
|
our_chip = to_samsung_pwm_chip(chip);
|
|
|
|
chip->ops = &pwm_samsung_ops;
|
|
our_chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
|
|
|
|
if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
|
|
ret = pwm_samsung_parse_dt(chip);
|
|
if (ret)
|
|
return ret;
|
|
} else {
|
|
if (!pdev->dev.platform_data)
|
|
return dev_err_probe(&pdev->dev, -EINVAL,
|
|
"no platform data specified\n");
|
|
|
|
memcpy(&our_chip->variant, pdev->dev.platform_data,
|
|
sizeof(our_chip->variant));
|
|
}
|
|
|
|
our_chip->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(our_chip->base))
|
|
return PTR_ERR(our_chip->base);
|
|
|
|
our_chip->base_clk = devm_clk_get_enabled(&pdev->dev, "timers");
|
|
if (IS_ERR(our_chip->base_clk))
|
|
return dev_err_probe(dev, PTR_ERR(our_chip->base_clk),
|
|
"failed to get timer base clk\n");
|
|
|
|
for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
|
|
if (our_chip->variant.output_mask & BIT(chan))
|
|
pwm_samsung_set_invert(our_chip, chan, true);
|
|
|
|
/* Following clocks are optional. */
|
|
our_chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
|
|
our_chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
|
|
|
|
platform_set_drvdata(pdev, chip);
|
|
|
|
ret = devm_pwmchip_add(&pdev->dev, chip);
|
|
if (ret < 0)
|
|
return dev_err_probe(dev, ret, "failed to register PWM chip\n");
|
|
|
|
dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
|
|
clk_get_rate(our_chip->base_clk),
|
|
!IS_ERR(our_chip->tclk0) ? clk_get_rate(our_chip->tclk0) : 0,
|
|
!IS_ERR(our_chip->tclk1) ? clk_get_rate(our_chip->tclk1) : 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pwm_samsung_resume(struct device *dev)
|
|
{
|
|
struct pwm_chip *chip = dev_get_drvdata(dev);
|
|
struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < SAMSUNG_PWM_NUM; i++) {
|
|
struct pwm_device *pwm = &chip->pwms[i];
|
|
struct samsung_pwm_channel *chan = &our_chip->channel[i];
|
|
|
|
if (!test_bit(PWMF_REQUESTED, &pwm->flags))
|
|
continue;
|
|
|
|
if (our_chip->variant.output_mask & BIT(i))
|
|
pwm_samsung_set_invert(our_chip, i,
|
|
our_chip->inverter_mask & BIT(i));
|
|
|
|
if (chan->period_ns) {
|
|
__pwm_samsung_config(chip, pwm, chan->duty_ns,
|
|
chan->period_ns, true);
|
|
/* needed to make PWM disable work on Odroid-XU3 */
|
|
pwm_samsung_manual_update(our_chip, pwm);
|
|
}
|
|
|
|
if (our_chip->disabled_mask & BIT(i))
|
|
pwm_samsung_disable(chip, pwm);
|
|
else
|
|
pwm_samsung_enable(chip, pwm);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static DEFINE_SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume);
|
|
|
|
static struct platform_driver pwm_samsung_driver = {
|
|
.driver = {
|
|
.name = "samsung-pwm",
|
|
.pm = pm_ptr(&pwm_samsung_pm_ops),
|
|
.of_match_table = of_match_ptr(samsung_pwm_matches),
|
|
},
|
|
.probe = pwm_samsung_probe,
|
|
};
|
|
module_platform_driver(pwm_samsung_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
|
|
MODULE_ALIAS("platform:samsung-pwm");
|