Clint Taylor 9659c1af45 drm/i915/icl: combo port vswing programming changes per BSPEC ... In August 2018 the BSPEC changed the ICL port programming sequence to closely resemble earlier gen programming sequence. Restrict combo phy to HBR max rate unless eDP panel is connected to port. v2: remove debug code that Imre found v3: simplify translation table if-else v4: edp translation table now based on link rate and low_swing v5: Misc review comments + r-b BSpec: 21257 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1545084827-5776-1-git-send-email-clinton.a.taylor@intel.com (cherry picked from commit b265a2a625) Signed-off-by: Jani Nikula <jani.nikula@intel.com>		2019-02-11 18:35:08 +02:00
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drm	drm/i915/icl: combo port vswing programming changes per BSPEC	2019-02-11 18:35:08 +02:00
host1x	gpu: host1x: Add Tegra194 support	2018-11-29 17:11:49 +01:00
ipu-v3	gpu: ipu-v3: image-convert: allow three rows or columns	2018-11-05 14:40:08 +01:00
vga	vga-switcheroo: make PCI dependency explicit	2019-01-15 23:16:47 +01:00
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