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cbb0c02caf
Dwarf based unwinding in a function that pushes SVE registers onto the stack requires the unwinder to know the length of the SVE register to calculate the stack offsets correctly. This was added to the Arm specific Dwarf spec as the VG pseudo register[1]. Add the vector length at position 46 if it's requested by userspace and SVE is supported. If it's not supported then fail to open the event. The vector length must be on each sample because it can be changed at runtime via a prctl or ptrace call. Also by adding it as a register rather than a separate attribute, minimal changes will be required in an unwinder that already indexes into the register list. [1]: https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst Reviewed-by: Mark Brown <broonie@kernel.org> Signed-off-by: James Clark <james.clark@arm.com> Link: https://lore.kernel.org/r/20220901132658.1024635-2-james.clark@arm.com Signed-off-by: Will Deacon <will@kernel.org>
107 lines
2.8 KiB
C
107 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/compat.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/perf_event.h>
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#include <linux/bug.h>
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#include <linux/sched/task_stack.h>
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#include <asm/perf_regs.h>
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#include <asm/ptrace.h>
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static u64 perf_ext_regs_value(int idx)
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{
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switch (idx) {
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case PERF_REG_ARM64_VG:
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if (WARN_ON_ONCE(!system_supports_sve()))
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return 0;
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/*
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* Vector granule is current length in bits of SVE registers
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* divided by 64.
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*/
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return (task_get_sve_vl(current) * 8) / 64;
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default:
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WARN_ON_ONCE(true);
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return 0;
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}
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}
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u64 perf_reg_value(struct pt_regs *regs, int idx)
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{
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if (WARN_ON_ONCE((u32)idx >= PERF_REG_ARM64_EXTENDED_MAX))
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return 0;
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/*
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* Our handling of compat tasks (PERF_SAMPLE_REGS_ABI_32) is weird, but
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* we're stuck with it for ABI compatibility reasons.
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*
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* For a 32-bit consumer inspecting a 32-bit task, then it will look at
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* the first 16 registers (see arch/arm/include/uapi/asm/perf_regs.h).
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* These correspond directly to a prefix of the registers saved in our
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* 'struct pt_regs', with the exception of the PC, so we copy that down
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* (x15 corresponds to SP_hyp in the architecture).
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*
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* So far, so good.
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*
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* The oddity arises when a 64-bit consumer looks at a 32-bit task and
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* asks for registers beyond PERF_REG_ARM_MAX. In this case, we return
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* SP_usr, LR_usr and PC in the positions where the AArch64 SP, LR and
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* PC registers would normally live. The initial idea was to allow a
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* 64-bit unwinder to unwind a 32-bit task and, although it's not clear
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* how well that works in practice, somebody might be relying on it.
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*
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* At the time we make a sample, we don't know whether the consumer is
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* 32-bit or 64-bit, so we have to cater for both possibilities.
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*/
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if (compat_user_mode(regs)) {
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if ((u32)idx == PERF_REG_ARM64_SP)
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return regs->compat_sp;
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if ((u32)idx == PERF_REG_ARM64_LR)
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return regs->compat_lr;
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if (idx == 15)
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return regs->pc;
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}
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if ((u32)idx == PERF_REG_ARM64_SP)
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return regs->sp;
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if ((u32)idx == PERF_REG_ARM64_PC)
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return regs->pc;
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if ((u32)idx >= PERF_REG_ARM64_MAX)
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return perf_ext_regs_value(idx);
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return regs->regs[idx];
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}
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#define REG_RESERVED (~((1ULL << PERF_REG_ARM64_MAX) - 1))
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int perf_reg_validate(u64 mask)
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{
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u64 reserved_mask = REG_RESERVED;
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if (system_supports_sve())
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reserved_mask &= ~(1ULL << PERF_REG_ARM64_VG);
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if (!mask || mask & reserved_mask)
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return -EINVAL;
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return 0;
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}
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u64 perf_reg_abi(struct task_struct *task)
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{
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if (is_compat_thread(task_thread_info(task)))
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return PERF_SAMPLE_REGS_ABI_32;
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else
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return PERF_SAMPLE_REGS_ABI_64;
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}
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void perf_get_regs_user(struct perf_regs *regs_user,
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struct pt_regs *regs)
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{
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regs_user->regs = task_pt_regs(current);
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regs_user->abi = perf_reg_abi(current);
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}
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