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1db1af84d6
This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
317 lines
6.4 KiB
ArmAsm
317 lines
6.4 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1994, 1995, 1996, by Andreas Busse
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) 2000 MIPS Technologies, Inc.
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* written by Carsten Langgaard, carstenl@mips.com
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*/
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#include <asm/asm.h>
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#include <asm/cachectl.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-bits.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#include <asm/thread_info.h>
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#include <asm/asmmacro.h>
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/*
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* Offset to the current process status flags, the first 32 bytes of the
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* stack are not used.
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*/
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#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
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/*
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* task_struct *resume(task_struct *prev, task_struct *next,
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* struct thread_info *next_ti, s32 fp_save)
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*/
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.align 5
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LEAF(resume)
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mfc0 t1, CP0_STATUS
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LONG_S t1, THREAD_STATUS(a0)
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cpu_save_nonscratch a0
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LONG_S ra, THREAD_REG31(a0)
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/*
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* Check whether we need to save any FP context. FP context is saved
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* iff the process has used the context with the scalar FPU or the MSA
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* ASE in the current time slice, as indicated by _TIF_USEDFPU and
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* _TIF_USEDMSA respectively. switch_to will have set fp_save
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* accordingly to an FP_SAVE_ enum value.
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*/
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beqz a3, 2f
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/*
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* We do. Clear the saved CU1 bit for prev, such that next time it is
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* scheduled it will start in userland with the FPU disabled. If the
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* task uses the FPU then it will be enabled again via the do_cpu trap.
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* This allows us to lazily restore the FP context.
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*/
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PTR_L t3, TASK_THREAD_INFO(a0)
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LONG_L t0, ST_OFF(t3)
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li t1, ~ST0_CU1
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and t0, t0, t1
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LONG_S t0, ST_OFF(t3)
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/* Check whether we're saving scalar or vector context. */
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bgtz a3, 1f
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/* Save 128b MSA vector context. */
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msa_save_all a0
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b 2f
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1: /* Save 32b/64b scalar FP context. */
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fpu_save_double a0 t0 t1 # c0_status passed in t0
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# clobbers t1
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2:
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#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
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PTR_LA t8, __stack_chk_guard
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LONG_L t9, TASK_STACK_CANARY(a1)
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LONG_S t9, 0(t8)
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#endif
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/*
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* The order of restoring the registers takes care of the race
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* updating $28, $29 and kernelsp without disabling ints.
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*/
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move $28, a2
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cpu_restore_nonscratch a1
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PTR_ADDU t0, $28, _THREAD_SIZE - 32
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set_saved_sp t0, t1, t2
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Read-modify-writes of Status must be atomic on a VPE */
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mfc0 t2, CP0_TCSTATUS
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ori t1, t2, TCSTATUS_IXMT
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mtc0 t1, CP0_TCSTATUS
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andi t2, t2, TCSTATUS_IXMT
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_ehb
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DMT 8 # dmt t0
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move t1,ra
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jal mips_ihb
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move ra,t1
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#endif /* CONFIG_MIPS_MT_SMTC */
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mfc0 t1, CP0_STATUS /* Do we really need this? */
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li a3, 0xff01
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and t1, a3
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LONG_L a2, THREAD_STATUS(a1)
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nor a3, $0, a3
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and a2, a3
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or a2, t1
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mtc0 a2, CP0_STATUS
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#ifdef CONFIG_MIPS_MT_SMTC
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_ehb
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andi t0, t0, VPECONTROL_TE
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beqz t0, 1f
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emt
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1:
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mfc0 t1, CP0_TCSTATUS
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xori t1, t1, TCSTATUS_IXMT
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or t1, t1, t2
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mtc0 t1, CP0_TCSTATUS
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_ehb
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#endif /* CONFIG_MIPS_MT_SMTC */
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move v0, a0
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jr ra
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END(resume)
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/*
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* Save a thread's fp context.
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*/
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LEAF(_save_fp)
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
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mfc0 t0, CP0_STATUS
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#endif
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fpu_save_double a0 t0 t1 # clobbers t1
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jr ra
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END(_save_fp)
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/*
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* Restore a thread's fp context.
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*/
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LEAF(_restore_fp)
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
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mfc0 t0, CP0_STATUS
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#endif
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fpu_restore_double a0 t0 t1 # clobbers t1
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jr ra
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END(_restore_fp)
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#ifdef CONFIG_CPU_HAS_MSA
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/*
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* Save a thread's MSA vector context.
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*/
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LEAF(_save_msa)
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msa_save_all a0
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jr ra
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END(_save_msa)
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/*
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* Restore a thread's MSA vector context.
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*/
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LEAF(_restore_msa)
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msa_restore_all a0
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jr ra
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END(_restore_msa)
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#endif
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/*
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* Load the FPU with signalling NANS. This bit pattern we're using has
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* the property that no matter whether considered as single or as double
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* precision represents signaling NANS.
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*
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* We initialize fcr31 to rounding to nearest, no exceptions.
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*/
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#define FPU_DEFAULT 0x00000000
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LEAF(_init_fpu)
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
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mfc0 t0, CP0_TCSTATUS
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/* Bit position is the same for Status, TCStatus */
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li t1, ST0_CU1
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or t0, t1
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mtc0 t0, CP0_TCSTATUS
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#else /* Normal MIPS CU1 enable */
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU1
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or t0, t1
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mtc0 t0, CP0_STATUS
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#endif /* CONFIG_MIPS_MT_SMTC */
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enable_fpu_hazard
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li t1, FPU_DEFAULT
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ctc1 t1, fcr31
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li t1, -1 # SNaN
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#ifdef CONFIG_64BIT
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sll t0, t0, 5
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bgez t0, 1f # 16 / 32 register mode?
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dmtc1 t1, $f1
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dmtc1 t1, $f3
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dmtc1 t1, $f5
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dmtc1 t1, $f7
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dmtc1 t1, $f9
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dmtc1 t1, $f11
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dmtc1 t1, $f13
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dmtc1 t1, $f15
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dmtc1 t1, $f17
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dmtc1 t1, $f19
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dmtc1 t1, $f21
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dmtc1 t1, $f23
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dmtc1 t1, $f25
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dmtc1 t1, $f27
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dmtc1 t1, $f29
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dmtc1 t1, $f31
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1:
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#endif
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#ifdef CONFIG_CPU_MIPS32
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mtc1 t1, $f0
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mtc1 t1, $f1
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mtc1 t1, $f2
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mtc1 t1, $f3
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mtc1 t1, $f4
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mtc1 t1, $f5
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mtc1 t1, $f6
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mtc1 t1, $f7
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mtc1 t1, $f8
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mtc1 t1, $f9
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mtc1 t1, $f10
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mtc1 t1, $f11
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mtc1 t1, $f12
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mtc1 t1, $f13
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mtc1 t1, $f14
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mtc1 t1, $f15
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mtc1 t1, $f16
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mtc1 t1, $f17
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mtc1 t1, $f18
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mtc1 t1, $f19
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mtc1 t1, $f20
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mtc1 t1, $f21
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mtc1 t1, $f22
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mtc1 t1, $f23
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mtc1 t1, $f24
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mtc1 t1, $f25
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mtc1 t1, $f26
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mtc1 t1, $f27
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mtc1 t1, $f28
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mtc1 t1, $f29
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mtc1 t1, $f30
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mtc1 t1, $f31
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#ifdef CONFIG_CPU_MIPS32_R2
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.set push
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.set mips64r2
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sll t0, t0, 5 # is Status.FR set?
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bgez t0, 1f # no: skip setting upper 32b
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mthc1 t1, $f0
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mthc1 t1, $f1
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mthc1 t1, $f2
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mthc1 t1, $f3
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mthc1 t1, $f4
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mthc1 t1, $f5
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mthc1 t1, $f6
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mthc1 t1, $f7
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mthc1 t1, $f8
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mthc1 t1, $f9
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mthc1 t1, $f10
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mthc1 t1, $f11
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mthc1 t1, $f12
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mthc1 t1, $f13
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mthc1 t1, $f14
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mthc1 t1, $f15
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mthc1 t1, $f16
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mthc1 t1, $f17
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mthc1 t1, $f18
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mthc1 t1, $f19
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mthc1 t1, $f20
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mthc1 t1, $f21
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mthc1 t1, $f22
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mthc1 t1, $f23
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mthc1 t1, $f24
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mthc1 t1, $f25
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mthc1 t1, $f26
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mthc1 t1, $f27
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mthc1 t1, $f28
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mthc1 t1, $f29
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mthc1 t1, $f30
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mthc1 t1, $f31
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1: .set pop
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#endif /* CONFIG_CPU_MIPS32_R2 */
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#else
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.set mips3
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dmtc1 t1, $f0
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dmtc1 t1, $f2
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dmtc1 t1, $f4
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dmtc1 t1, $f6
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dmtc1 t1, $f8
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dmtc1 t1, $f10
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dmtc1 t1, $f12
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dmtc1 t1, $f14
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dmtc1 t1, $f16
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dmtc1 t1, $f18
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dmtc1 t1, $f20
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dmtc1 t1, $f22
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dmtc1 t1, $f24
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dmtc1 t1, $f26
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dmtc1 t1, $f28
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dmtc1 t1, $f30
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#endif
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jr ra
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END(_init_fpu)
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