mirror of
https://github.com/torvalds/linux
synced 2024-11-05 18:23:50 +00:00
393 lines
11 KiB
ArmAsm
393 lines
11 KiB
ArmAsm
/*
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* Event entry/exit for Hexagon
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*
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* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <asm/asm-offsets.h> /* assembly-safer versions of C defines */
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#include <asm/mem-layout.h> /* sigh, except for page_offset */
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#include <asm/hexagon_vm.h>
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#include <asm/thread_info.h>
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/*
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* Entry into guest-mode Linux under Hexagon Virtual Machine.
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* Stack pointer points to event record - build pt_regs on top of it,
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* set up a plausible C stack frame, and dispatch to the C handler.
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* On return, do vmrte virtual instruction with SP where we started.
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*
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* VM Spec 0.5 uses a trap to fetch HVM record now.
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*/
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/*
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* Save full register state, while setting up thread_info struct
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* pointer derived from kernel stack pointer in THREADINFO_REG
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* register, putting prior thread_info.regs pointer in a callee-save
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* register (R24, which had better not ever be assigned to THREADINFO_REG),
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* and updating thread_info.regs to point to current stack frame,
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* so as to support nested events in kernel mode.
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*
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* As this is common code, we set the pt_regs system call number
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* to -1 for all events. It will be replaced with the system call
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* number in the case where we decode a system call (trap0(#1)).
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*/
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#if CONFIG_HEXAGON_ARCH_VERSION < 4
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#define save_pt_regs()\
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memd(R0 + #_PT_R3130) = R31:30; \
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{ memw(R0 + #_PT_R2928) = R28; \
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R31 = memw(R0 + #_PT_ER_VMPSP); }\
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{ memw(R0 + #(_PT_R2928 + 4)) = R31; \
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R31 = ugp; } \
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{ memd(R0 + #_PT_R2726) = R27:26; \
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R30 = gp ; } \
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memd(R0 + #_PT_R2524) = R25:24; \
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memd(R0 + #_PT_R2322) = R23:22; \
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memd(R0 + #_PT_R2120) = R21:20; \
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memd(R0 + #_PT_R1918) = R19:18; \
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memd(R0 + #_PT_R1716) = R17:16; \
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memd(R0 + #_PT_R1514) = R15:14; \
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memd(R0 + #_PT_R1312) = R13:12; \
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{ memd(R0 + #_PT_R1110) = R11:10; \
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R15 = lc0; } \
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{ memd(R0 + #_PT_R0908) = R9:8; \
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R14 = sa0; } \
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{ memd(R0 + #_PT_R0706) = R7:6; \
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R13 = lc1; } \
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{ memd(R0 + #_PT_R0504) = R5:4; \
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R12 = sa1; } \
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{ memd(R0 + #_PT_GPUGP) = R31:30; \
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R11 = m1; \
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R2.H = #HI(_THREAD_SIZE); } \
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{ memd(R0 + #_PT_LC0SA0) = R15:14; \
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R10 = m0; \
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R2.L = #LO(_THREAD_SIZE); } \
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{ memd(R0 + #_PT_LC1SA1) = R13:12; \
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R15 = p3:0; \
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R2 = neg(R2); } \
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{ memd(R0 + #_PT_M1M0) = R11:10; \
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R14 = usr; \
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R2 = and(R0,R2); } \
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{ memd(R0 + #_PT_PREDSUSR) = R15:14; \
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THREADINFO_REG = R2; } \
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{ r24 = memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS); \
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memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
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R2 = #-1; } \
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{ memw(R0 + #_PT_SYSCALL_NR) = R2; \
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R30 = #0; }
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#else
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/* V4+ */
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/* the # ## # syntax inserts a literal ## */
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#define save_pt_regs()\
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{ memd(R0 + #_PT_R3130) = R31:30; \
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R30 = memw(R0 + #_PT_ER_VMPSP); }\
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{ memw(R0 + #_PT_R2928) = R28; \
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memw(R0 + #(_PT_R2928 + 4)) = R30; }\
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{ R31:30 = C11:10; \
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memd(R0 + #_PT_R2726) = R27:26; \
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memd(R0 + #_PT_R2524) = R25:24; }\
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{ memd(R0 + #_PT_R2322) = R23:22; \
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memd(R0 + #_PT_R2120) = R21:20; }\
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{ memd(R0 + #_PT_R1918) = R19:18; \
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memd(R0 + #_PT_R1716) = R17:16; }\
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{ memd(R0 + #_PT_R1514) = R15:14; \
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memd(R0 + #_PT_R1312) = R13:12; \
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R17:16 = C13:12; }\
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{ memd(R0 + #_PT_R1110) = R11:10; \
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memd(R0 + #_PT_R0908) = R9:8; \
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R15:14 = C1:0; } \
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{ memd(R0 + #_PT_R0706) = R7:6; \
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memd(R0 + #_PT_R0504) = R5:4; \
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R13:12 = C3:2; } \
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{ memd(R0 + #_PT_GPUGP) = R31:30; \
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memd(R0 + #_PT_LC0SA0) = R15:14; \
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R11:10 = C7:6; }\
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{ THREADINFO_REG = and(R0, # ## #-_THREAD_SIZE); \
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memd(R0 + #_PT_LC1SA1) = R13:12; \
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R15 = p3:0; }\
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{ memd(R0 + #_PT_M1M0) = R11:10; \
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memw(R0 + #_PT_PREDSUSR + 4) = R15; }\
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{ r24 = memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS); \
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memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
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R2 = #-1; } \
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{ memw(R0 + #_PT_SYSCALL_NR) = R2; \
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memd(R0 + #_PT_CS1CS0) = R17:16; \
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R30 = #0; }
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#endif
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/*
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* Restore registers and thread_info.regs state. THREADINFO_REG
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* is assumed to still be sane, and R24 to have been correctly
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* preserved. Don't restore R29 (SP) until later.
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*/
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#if CONFIG_HEXAGON_ARCH_VERSION < 4
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#define restore_pt_regs() \
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{ memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R24; \
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R15:14 = memd(R0 + #_PT_PREDSUSR); } \
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{ R11:10 = memd(R0 + #_PT_M1M0); \
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p3:0 = R15; } \
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{ R13:12 = memd(R0 + #_PT_LC1SA1); \
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usr = R14; } \
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{ R15:14 = memd(R0 + #_PT_LC0SA0); \
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m1 = R11; } \
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{ R3:2 = memd(R0 + #_PT_R0302); \
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m0 = R10; } \
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{ R5:4 = memd(R0 + #_PT_R0504); \
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lc1 = R13; } \
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{ R7:6 = memd(R0 + #_PT_R0706); \
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sa1 = R12; } \
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{ R9:8 = memd(R0 + #_PT_R0908); \
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lc0 = R15; } \
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{ R11:10 = memd(R0 + #_PT_R1110); \
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sa0 = R14; } \
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{ R13:12 = memd(R0 + #_PT_R1312); \
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R15:14 = memd(R0 + #_PT_R1514); } \
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{ R17:16 = memd(R0 + #_PT_R1716); \
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R19:18 = memd(R0 + #_PT_R1918); } \
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{ R21:20 = memd(R0 + #_PT_R2120); \
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R23:22 = memd(R0 + #_PT_R2322); } \
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{ R25:24 = memd(R0 + #_PT_R2524); \
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R27:26 = memd(R0 + #_PT_R2726); } \
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R31:30 = memd(R0 + #_PT_GPUGP); \
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{ R28 = memw(R0 + #_PT_R2928); \
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ugp = R31; } \
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{ R31:30 = memd(R0 + #_PT_R3130); \
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gp = R30; }
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#else
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/* V4+ */
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#define restore_pt_regs() \
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{ memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R24; \
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R15:14 = memd(R0 + #_PT_PREDSUSR); } \
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{ R11:10 = memd(R0 + #_PT_M1M0); \
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R13:12 = memd(R0 + #_PT_LC1SA1); \
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p3:0 = R15; } \
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{ R15:14 = memd(R0 + #_PT_LC0SA0); \
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R3:2 = memd(R0 + #_PT_R0302); \
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usr = R14; } \
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{ R5:4 = memd(R0 + #_PT_R0504); \
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R7:6 = memd(R0 + #_PT_R0706); \
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C7:6 = R11:10; }\
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{ R9:8 = memd(R0 + #_PT_R0908); \
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R11:10 = memd(R0 + #_PT_R1110); \
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C3:2 = R13:12; }\
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{ R13:12 = memd(R0 + #_PT_R1312); \
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R15:14 = memd(R0 + #_PT_R1514); \
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C1:0 = R15:14; }\
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{ R17:16 = memd(R0 + #_PT_R1716); \
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R19:18 = memd(R0 + #_PT_R1918); } \
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{ R21:20 = memd(R0 + #_PT_R2120); \
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R23:22 = memd(R0 + #_PT_R2322); } \
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{ R25:24 = memd(R0 + #_PT_R2524); \
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R27:26 = memd(R0 + #_PT_R2726); } \
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R31:30 = memd(R0 + #_PT_CS1CS0); \
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{ C13:12 = R31:30; \
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R31:30 = memd(R0 + #_PT_GPUGP) ; \
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R28 = memw(R0 + #_PT_R2928); }\
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{ C11:10 = R31:30; \
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R31:30 = memd(R0 + #_PT_R3130); }
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#endif
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/*
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* Clears off enough space for the rest of pt_regs; evrec is a part
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* of pt_regs in HVM mode. Save R0/R1, set handler's address in R1.
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* R0 is the address of pt_regs and is the parameter to save_pt_regs.
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*/
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/*
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* Since the HVM isn't automagically pushing the EVREC onto the stack anymore,
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* we'll subract the entire size out and then fill it in ourselves.
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* Need to save off R0, R1, R2, R3 immediately.
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*/
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#if CONFIG_HEXAGON_ARCH_VERSION < 4
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#define vm_event_entry(CHandler) \
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{ \
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R29 = add(R29, #-(_PT_REGS_SIZE)); \
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memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
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} \
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{ \
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memd(R29 +#_PT_R0302) = R3:2; \
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} \
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trap1(#HVM_TRAP1_VMGETREGS); \
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{ \
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memd(R29 + #_PT_ER_VMEL) = R1:0; \
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R0 = R29; \
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R1.L = #LO(CHandler); \
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} \
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{ \
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memd(R29 + #_PT_ER_VMPSP) = R3:2; \
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R1.H = #HI(CHandler); \
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jump event_dispatch; \
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}
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#else
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/* V4+ */
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/* turn on I$ prefetch early */
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/* the # ## # syntax inserts a literal ## */
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#define vm_event_entry(CHandler) \
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{ \
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R29 = add(R29, #-(_PT_REGS_SIZE)); \
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memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
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memd(R29 + #(_PT_R0302 + -_PT_REGS_SIZE)) = R3:2; \
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R0 = usr; \
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} \
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{ \
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memw(R29 + #_PT_PREDSUSR) = R0; \
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R0 = setbit(R0, #16); \
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} \
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usr = R0; \
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R1:0 = G1:0; \
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{ \
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memd(R29 + #_PT_ER_VMEL) = R1:0; \
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R1 = # ## #(CHandler); \
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R3:2 = G3:2; \
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} \
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{ \
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R0 = R29; \
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memd(R29 + #_PT_ER_VMPSP) = R3:2; \
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jump event_dispatch; \
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}
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#endif
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.text
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/*
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* Do bulk save/restore in one place.
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* Adds a jump to dispatch latency, but
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* saves hundreds of bytes.
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*/
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event_dispatch:
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save_pt_regs()
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callr r1
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/*
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* Coming back from the C-world, our thread info pointer
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* should be in the designated register (usually R19)
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*
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* If we were in kernel mode, we don't need to check scheduler
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* or signals if CONFIG_PREEMPT is not set. If set, then it has
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* to jump to a need_resched kind of block.
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* BTW, CONFIG_PREEMPT is not supported yet.
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*/
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#ifdef CONFIG_PREEMPT
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R0 = #VM_INT_DISABLE
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trap1(#HVM_TRAP1_VMSETIE)
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#endif
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/* "Nested control path" -- if the previous mode was kernel */
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{
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R0 = memw(R29 + #_PT_ER_VMEST);
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R26.L = #LO(do_work_pending);
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}
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{
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P0 = tstbit(R0, #HVM_VMEST_UM_SFT);
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if (!P0.new) jump:nt restore_all;
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R26.H = #HI(do_work_pending);
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R0 = #VM_INT_DISABLE;
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}
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/*
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* Check also the return from fork/system call, normally coming back from
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* user mode
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*
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* R26 needs to have do_work_pending, and R0 should have VM_INT_DISABLE
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*/
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check_work_pending:
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/* Disable interrupts while checking TIF */
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trap1(#HVM_TRAP1_VMSETIE)
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{
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R0 = R29; /* regs should still be at top of stack */
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R1 = memw(THREADINFO_REG + #_THREAD_INFO_FLAGS);
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callr R26;
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}
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{
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P0 = cmp.eq(R0, #0); if (!P0.new) jump:nt check_work_pending;
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R0 = #VM_INT_DISABLE;
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}
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restore_all:
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/*
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* Disable interrupts, if they weren't already, before reg restore.
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* R0 gets preloaded with #VM_INT_DISABLE before we get here.
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*/
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trap1(#HVM_TRAP1_VMSETIE)
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/* do the setregs here for VM 0.5 */
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/* R29 here should already be pointing at pt_regs */
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{
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R1:0 = memd(R29 + #_PT_ER_VMEL);
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R3:2 = memd(R29 + #_PT_ER_VMPSP);
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}
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#if CONFIG_HEXAGON_ARCH_VERSION < 4
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trap1(#HVM_TRAP1_VMSETREGS);
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#else
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G1:0 = R1:0;
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G3:2 = R3:2;
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#endif
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R0 = R29
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restore_pt_regs()
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{
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R1:0 = memd(R29 + #_PT_R0100);
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R29 = add(R29, #_PT_REGS_SIZE);
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}
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trap1(#HVM_TRAP1_VMRTE)
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/* Notreached */
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.globl _K_enter_genex
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_K_enter_genex:
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vm_event_entry(do_genex)
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.globl _K_enter_interrupt
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_K_enter_interrupt:
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vm_event_entry(arch_do_IRQ)
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.globl _K_enter_trap0
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_K_enter_trap0:
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vm_event_entry(do_trap0)
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.globl _K_enter_machcheck
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_K_enter_machcheck:
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vm_event_entry(do_machcheck)
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.globl _K_enter_debug
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_K_enter_debug:
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vm_event_entry(do_debug_exception)
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.globl ret_from_fork
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ret_from_fork:
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{
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call schedule_tail
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R26.H = #HI(do_work_pending);
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}
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{
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P0 = cmp.eq(R24, #0);
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R26.L = #LO(do_work_pending);
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R0 = #VM_INT_DISABLE;
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}
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if P0 jump check_work_pending
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{
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R0 = R25;
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callr R24
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}
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{
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jump check_work_pending
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R0 = #VM_INT_DISABLE;
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}
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