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The CSI2RX subsystem uses PSI-L DMA to transfer frames to memory. It can have up to 32 threads per instance. J721S2 has two instances of the subsystem, so there are 64 threads total, Add them to the endpoint map. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20240125111449.855876-1-vaishnav.a@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
260 lines
5.8 KiB
C
260 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
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*/
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#include <linux/kernel.h>
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#include "k3-psil-priv.h"
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#define PSIL_PDMA_XY_TR(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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}, \
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}
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#define PSIL_PDMA_XY_PKT(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pkt_mode = 1, \
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}, \
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}
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#define PSIL_PDMA_MCASP(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pdma_acc32 = 1, \
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.pdma_burst = 1, \
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}, \
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}
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#define PSIL_ETHERNET(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 16, \
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}, \
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}
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#define PSIL_SA2UL(x, tx) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 64, \
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.notdpkt = tx, \
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}, \
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}
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#define PSIL_CSI2RX(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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}, \
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}
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/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
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static struct psil_ep j721s2_src_ep_map[] = {
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/* PDMA_MCASP - McASP0-4 */
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PSIL_PDMA_MCASP(0x4400),
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PSIL_PDMA_MCASP(0x4401),
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PSIL_PDMA_MCASP(0x4402),
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PSIL_PDMA_MCASP(0x4403),
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PSIL_PDMA_MCASP(0x4404),
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/* PDMA_SPI_G0 - SPI0-3 */
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PSIL_PDMA_XY_PKT(0x4600),
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PSIL_PDMA_XY_PKT(0x4601),
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PSIL_PDMA_XY_PKT(0x4602),
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PSIL_PDMA_XY_PKT(0x4603),
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PSIL_PDMA_XY_PKT(0x4604),
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PSIL_PDMA_XY_PKT(0x4605),
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PSIL_PDMA_XY_PKT(0x4606),
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PSIL_PDMA_XY_PKT(0x4607),
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PSIL_PDMA_XY_PKT(0x4608),
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PSIL_PDMA_XY_PKT(0x4609),
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PSIL_PDMA_XY_PKT(0x460a),
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PSIL_PDMA_XY_PKT(0x460b),
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PSIL_PDMA_XY_PKT(0x460c),
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PSIL_PDMA_XY_PKT(0x460d),
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PSIL_PDMA_XY_PKT(0x460e),
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PSIL_PDMA_XY_PKT(0x460f),
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/* PDMA_SPI_G1 - SPI4-7 */
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PSIL_PDMA_XY_PKT(0x4610),
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PSIL_PDMA_XY_PKT(0x4611),
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PSIL_PDMA_XY_PKT(0x4612),
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PSIL_PDMA_XY_PKT(0x4613),
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PSIL_PDMA_XY_PKT(0x4614),
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PSIL_PDMA_XY_PKT(0x4615),
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PSIL_PDMA_XY_PKT(0x4616),
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PSIL_PDMA_XY_PKT(0x4617),
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PSIL_PDMA_XY_PKT(0x4618),
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PSIL_PDMA_XY_PKT(0x4619),
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PSIL_PDMA_XY_PKT(0x461a),
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PSIL_PDMA_XY_PKT(0x461b),
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PSIL_PDMA_XY_PKT(0x461c),
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PSIL_PDMA_XY_PKT(0x461d),
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PSIL_PDMA_XY_PKT(0x461e),
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PSIL_PDMA_XY_PKT(0x461f),
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/* MAIN_CPSW2G */
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PSIL_ETHERNET(0x4640),
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/* PDMA_USART_G0 - UART0-1 */
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PSIL_PDMA_XY_PKT(0x4700),
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PSIL_PDMA_XY_PKT(0x4701),
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/* PDMA_USART_G1 - UART2-3 */
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PSIL_PDMA_XY_PKT(0x4702),
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PSIL_PDMA_XY_PKT(0x4703),
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/* PDMA_USART_G2 - UART4-9 */
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PSIL_PDMA_XY_PKT(0x4704),
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PSIL_PDMA_XY_PKT(0x4705),
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PSIL_PDMA_XY_PKT(0x4706),
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PSIL_PDMA_XY_PKT(0x4707),
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PSIL_PDMA_XY_PKT(0x4708),
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PSIL_PDMA_XY_PKT(0x4709),
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/* CSI2RX */
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PSIL_CSI2RX(0x4940),
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PSIL_CSI2RX(0x4941),
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PSIL_CSI2RX(0x4942),
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PSIL_CSI2RX(0x4943),
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PSIL_CSI2RX(0x4944),
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PSIL_CSI2RX(0x4945),
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PSIL_CSI2RX(0x4946),
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PSIL_CSI2RX(0x4947),
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PSIL_CSI2RX(0x4948),
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PSIL_CSI2RX(0x4949),
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PSIL_CSI2RX(0x494a),
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PSIL_CSI2RX(0x494b),
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PSIL_CSI2RX(0x494c),
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PSIL_CSI2RX(0x494d),
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PSIL_CSI2RX(0x494e),
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PSIL_CSI2RX(0x494f),
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PSIL_CSI2RX(0x4950),
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PSIL_CSI2RX(0x4951),
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PSIL_CSI2RX(0x4952),
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PSIL_CSI2RX(0x4953),
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PSIL_CSI2RX(0x4954),
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PSIL_CSI2RX(0x4955),
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PSIL_CSI2RX(0x4956),
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PSIL_CSI2RX(0x4957),
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PSIL_CSI2RX(0x4958),
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PSIL_CSI2RX(0x4959),
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PSIL_CSI2RX(0x495a),
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PSIL_CSI2RX(0x495b),
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PSIL_CSI2RX(0x495c),
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PSIL_CSI2RX(0x495d),
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PSIL_CSI2RX(0x495e),
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PSIL_CSI2RX(0x495f),
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PSIL_CSI2RX(0x4960),
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PSIL_CSI2RX(0x4961),
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PSIL_CSI2RX(0x4962),
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PSIL_CSI2RX(0x4963),
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PSIL_CSI2RX(0x4964),
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PSIL_CSI2RX(0x4965),
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PSIL_CSI2RX(0x4966),
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PSIL_CSI2RX(0x4967),
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PSIL_CSI2RX(0x4968),
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PSIL_CSI2RX(0x4969),
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PSIL_CSI2RX(0x496a),
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PSIL_CSI2RX(0x496b),
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PSIL_CSI2RX(0x496c),
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PSIL_CSI2RX(0x496d),
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PSIL_CSI2RX(0x496e),
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PSIL_CSI2RX(0x496f),
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PSIL_CSI2RX(0x4970),
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PSIL_CSI2RX(0x4971),
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PSIL_CSI2RX(0x4972),
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PSIL_CSI2RX(0x4973),
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PSIL_CSI2RX(0x4974),
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PSIL_CSI2RX(0x4975),
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PSIL_CSI2RX(0x4976),
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PSIL_CSI2RX(0x4977),
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PSIL_CSI2RX(0x4978),
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PSIL_CSI2RX(0x4979),
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PSIL_CSI2RX(0x497a),
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PSIL_CSI2RX(0x497b),
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PSIL_CSI2RX(0x497c),
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PSIL_CSI2RX(0x497d),
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PSIL_CSI2RX(0x497e),
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PSIL_CSI2RX(0x497f),
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/* MAIN SA2UL */
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PSIL_SA2UL(0x4a40, 0),
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PSIL_SA2UL(0x4a41, 0),
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PSIL_SA2UL(0x4a42, 0),
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PSIL_SA2UL(0x4a43, 0),
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/* CPSW0 */
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PSIL_ETHERNET(0x7000),
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/* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
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PSIL_PDMA_XY_PKT(0x7100),
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PSIL_PDMA_XY_PKT(0x7101),
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PSIL_PDMA_XY_PKT(0x7102),
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PSIL_PDMA_XY_PKT(0x7103),
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/* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
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PSIL_PDMA_XY_PKT(0x7200),
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PSIL_PDMA_XY_PKT(0x7201),
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PSIL_PDMA_XY_PKT(0x7202),
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PSIL_PDMA_XY_PKT(0x7203),
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PSIL_PDMA_XY_PKT(0x7204),
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PSIL_PDMA_XY_PKT(0x7205),
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PSIL_PDMA_XY_PKT(0x7206),
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PSIL_PDMA_XY_PKT(0x7207),
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/* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
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PSIL_PDMA_XY_PKT(0x7300),
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/* MCU_PDMA_ADC - ADC0-1 */
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PSIL_PDMA_XY_TR(0x7400),
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PSIL_PDMA_XY_TR(0x7401),
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PSIL_PDMA_XY_TR(0x7402),
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PSIL_PDMA_XY_TR(0x7403),
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/* SA2UL */
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PSIL_SA2UL(0x7500, 0),
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PSIL_SA2UL(0x7501, 0),
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PSIL_SA2UL(0x7502, 0),
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PSIL_SA2UL(0x7503, 0),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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static struct psil_ep j721s2_dst_ep_map[] = {
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/* MAIN SA2UL */
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PSIL_SA2UL(0xca40, 1),
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PSIL_SA2UL(0xca41, 1),
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/* CPSW0 */
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PSIL_ETHERNET(0xf000),
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PSIL_ETHERNET(0xf001),
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PSIL_ETHERNET(0xf002),
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PSIL_ETHERNET(0xf003),
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PSIL_ETHERNET(0xf004),
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PSIL_ETHERNET(0xf005),
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PSIL_ETHERNET(0xf006),
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PSIL_ETHERNET(0xf007),
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/* MAIN_CPSW2G */
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PSIL_ETHERNET(0xc640),
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PSIL_ETHERNET(0xc641),
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PSIL_ETHERNET(0xc642),
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PSIL_ETHERNET(0xc643),
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PSIL_ETHERNET(0xc644),
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PSIL_ETHERNET(0xc645),
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PSIL_ETHERNET(0xc646),
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PSIL_ETHERNET(0xc647),
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/* SA2UL */
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PSIL_SA2UL(0xf500, 1),
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PSIL_SA2UL(0xf501, 1),
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};
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struct psil_ep_map j721s2_ep_map = {
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.name = "j721s2",
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.src = j721s2_src_ep_map,
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.src_count = ARRAY_SIZE(j721s2_src_ep_map),
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.dst = j721s2_dst_ep_map,
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.dst_count = ARRAY_SIZE(j721s2_dst_ep_map),
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};
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