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8c690fdf46
The ports are used as follows: UART1/A: Routed to debug dongle UART2/B: GPS UART3/C: Bluetooth UART4/D: Routed to debug dongle UART5/E: Not connected The debug dongle has jumpers to connect either UART1/A or UART4/D to the DB-9 connector. UART1/A is typically used on Cardhu, and is the option we assume here. For now, only enable UART1/A, and explicitly disable all other ports. The explicit disable prevents the message "of_serial 70006040.serial: no clock-frequency property set" being printed during boot. Enabling the other ports requires their clocks to be enabled, or accesses to the registers will hang. At present, this requires adding entries into board-dt-tegra30.c's tegra_dt_clk_init_table[]. Lets punt on that and wait for the common clock bindings to set this all up, although that will also requiring adding clock support to 8250.c. While we're at it, fix board-dt-tegra30.c to enable the correct clock for the debug UART. We got away with this before, because the bootloader already enabled it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
53 lines
692 B
Plaintext
53 lines
692 B
Plaintext
/dts-v1/;
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/include/ "tegra30.dtsi"
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/ {
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model = "NVIDIA Tegra30 Cardhu evaluation board";
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compatible = "nvidia,cardhu", "nvidia,tegra30";
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memory {
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reg = < 0x80000000 0x40000000 >;
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};
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serial@70006000 {
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clock-frequency = < 408000000 >;
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};
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serial@70006040 {
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status = "disable";
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};
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serial@70006200 {
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status = "disable";
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};
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serial@70006300 {
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status = "disable";
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};
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serial@70006400 {
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status = "disable";
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};
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i2c@7000c000 {
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clock-frequency = <100000>;
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};
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i2c@7000c400 {
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clock-frequency = <100000>;
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};
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i2c@7000c500 {
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clock-frequency = <100000>;
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};
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i2c@7000c700 {
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clock-frequency = <100000>;
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};
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i2c@7000d000 {
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clock-frequency = <100000>;
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};
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};
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