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https://github.com/torvalds/linux
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8c3583b634
instead of reading the registers everytime the current implementation respect the following constrain: - allow 1 to n soc to be enabled - allow to have a virtual cpu type and subtype - always detect the cpu type and subtype and report it - detect if the soc support is enabled - prepare for sysfs export support - drop soc specific code via compiler when the soc not enabled (via cpu_is_xxx) Today if we read the exid we will have the same value for 9g35 and 9m11 and we will need to check the cidr too with the new implementation we just need to check the soc subtype this will also allow to have specific virtual subtype for rm9200 which the board will have to specify via at91rm9200_set_type(int) as we have no way to detect it. this implementation is inspired by the SH cpu detection support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
380 lines
9.4 KiB
C
380 lines
9.4 KiB
C
/*
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* arch/arm/mach-at91/at91sam9263.c
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*
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* Copyright (C) 2007 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/at91sam9263.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_rstc.h>
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#include <mach/at91_shdwc.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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static struct map_desc at91sam9263_sram_desc[] __initdata = {
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{
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.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
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.pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
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.length = AT91SAM9263_SRAM0_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
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.pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
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.length = AT91SAM9263_SRAM1_SIZE,
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.type = MT_DEVICE,
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},
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};
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioCDE_clk = {
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.name = "pioCDE_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc0_clk = {
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.name = "mci0_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc1_clk = {
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.name = "mci1_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk can_clk = {
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.name = "can_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_CAN,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi_clk = {
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.name = "twi_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_TWI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ac97_clk = {
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.name = "ac97_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_AC97C,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb_clk = {
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.name = "tcb_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk macb_clk = {
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.name = "macb_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twodge_clk = {
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.name = "2dge_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_2DGE,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udc_clk = {
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.name = "udc_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_UDP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_UHP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioCDE_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&mmc0_clk,
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&mmc1_clk,
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&can_clk,
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&twi_clk,
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&spi0_clk,
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&spi1_clk,
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&ssc0_clk,
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&ssc1_clk,
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&ac97_clk,
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&tcb_clk,
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&pwm_clk,
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&macb_clk,
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&twodge_clk,
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&udc_clk,
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&isi_clk,
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&lcdc_clk,
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&dma_clk,
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&ohci_clk,
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// irq0 .. irq1
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
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};
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/*
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* The four programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static struct clk pck2 = {
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.name = "pck2",
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.pmc_mask = AT91_PMC_PCK2,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 2,
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};
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static struct clk pck3 = {
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.name = "pck3",
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.pmc_mask = AT91_PMC_PCK3,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 3,
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};
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static void __init at91sam9263_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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clk_register(&pck0);
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clk_register(&pck1);
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clk_register(&pck2);
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clk_register(&pck3);
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}
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static struct clk_lookup console_clock_lookup;
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void __init at91sam9263_set_console_clock(int id)
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{
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if (id >= ARRAY_SIZE(usart_clocks_lookups))
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return;
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console_clock_lookup.con_id = "usart";
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console_clock_lookup.clk = usart_clocks_lookups[id].clk;
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clkdev_add(&console_clock_lookup);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9263_gpio[] = {
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{
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.id = AT91SAM9263_ID_PIOA,
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.offset = AT91_PIOA,
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.clock = &pioA_clk,
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}, {
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.id = AT91SAM9263_ID_PIOB,
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.offset = AT91_PIOB,
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.clock = &pioB_clk,
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}, {
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.id = AT91SAM9263_ID_PIOCDE,
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.offset = AT91_PIOC,
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.clock = &pioCDE_clk,
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}, {
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.id = AT91SAM9263_ID_PIOCDE,
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.offset = AT91_PIOD,
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.clock = &pioCDE_clk,
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}, {
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.id = AT91SAM9263_ID_PIOCDE,
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.offset = AT91_PIOE,
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.clock = &pioCDE_clk,
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}
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};
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static void at91sam9263_poweroff(void)
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{
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at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
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}
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/* --------------------------------------------------------------------
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* AT91SAM9263 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9263_map_io(void)
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{
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iotable_init(at91sam9263_sram_desc, ARRAY_SIZE(at91sam9263_sram_desc));
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}
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static void __init at91sam9263_initialize(unsigned long main_clock)
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{
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at91_arch_reset = at91sam9_alt_reset;
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pm_power_off = at91sam9263_poweroff;
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at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
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/* Init clock subsystem */
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at91_clock_init(main_clock);
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/* Register the processor-specific clocks */
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at91sam9263_register_clocks();
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9263_gpio, 5);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller (FIQ) */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C, D and E */
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0,
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0,
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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0, /* Multimedia Card Interface 0 */
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0, /* Multimedia Card Interface 1 */
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3, /* CAN */
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6, /* Two-Wire Interface */
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5, /* Serial Peripheral Interface 0 */
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5, /* Serial Peripheral Interface 1 */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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5, /* AC97 Controller */
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0, /* Timer Counter 0, 1 and 2 */
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0, /* Pulse Width Modulation Controller */
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3, /* Ethernet */
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0,
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0, /* 2D Graphic Engine */
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2, /* USB Device Port */
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0, /* Image Sensor Interface */
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3, /* LDC Controller */
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0, /* DMA Controller */
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0,
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2, /* USB Host port */
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0, /* Advanced Interrupt Controller (IRQ0) */
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0, /* Advanced Interrupt Controller (IRQ1) */
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};
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struct at91_init_soc __initdata at91sam9263_soc = {
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.map_io = at91sam9263_map_io,
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.default_irq_priority = at91sam9263_default_irq_priority,
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.init = at91sam9263_initialize,
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};
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