Marc Zyngier 8892b71885 arm64: capabilities: Rework EL2 vector hardening entry ... Since 5e7951ce19 ("arm64: capabilities: Clean up midr range helpers"), capabilities must be represented with a single entry. If multiple CPU types can use the same capability, then they need to be enumerated in a list. The EL2 hardening stuff (which affects both A57 and A72) managed to escape the conversion in the above patch thanks to the 4.17 merge window. Let's fix it now. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>		2018-04-11 18:49:30 +01:00
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boot	ARM: SoC device tree updates for 4.17	2018-04-05 21:18:09 -07:00
configs	arm64: defconfig: add CONFIG_UNIPHIER_THERMAL and CONFIG_SNI_AVE	2018-03-27 15:31:19 +02:00
crypto	crypto: arm,arm64 - Fix random regeneration of S_shipped	2018-03-23 23:43:19 +08:00
include	arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening	2018-04-11 18:49:30 +01:00
kernel	arm64: capabilities: Rework EL2 vector hardening entry	2018-04-11 18:49:30 +01:00
kvm	arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening	2018-04-11 18:49:30 +01:00
lib	DeviceTree updates for 4.17:	2018-04-05 21:03:42 -07:00
mm	arm64 updates for 4.17	2018-04-04 16:01:43 -07:00
net	bpf, arm64: fix out of bounds access in tail call	2018-02-22 16:06:28 -08:00
xen	arm64: mm: Add additional parameter to uaccess_ttbr0_disable	2018-01-17 13:57:49 +01:00
Kconfig	ARM:	2018-04-09 11:42:31 -07:00
Kconfig.debug
Kconfig.platforms	arm64: add Renesas R8A77965 support	2018-03-13 19:05:58 +01:00
Makefile	arm64/kernel: don't ban ADRP to work around Cortex-A53 erratum #843419	2018-03-09 13:21:53 +00:00