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8718455472
As QAM_64, QAM_256, and QAM_AUTO all use the same firmware, switching between these modulations doesn't require a firmware re-load. This also fixes a mishandled error condition, in which the firmware file is loaded into the kernel, the clock mode is changed, but then the firmware upload to the device fails. The modulation change is aborted, but the clock mode would still be changed. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org> Signed-off-by: Andrew de Quincey <adq_dvb@lidskialf.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
646 lines
18 KiB
C
646 lines
18 KiB
C
/*
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* Support for OR51132 (pcHDTV HD-3000) - VSB/QAM
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*
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* Copyright (C) 2005 Kirk Lapray <kirk_lapray@bigfoot.com>
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*
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* Based on code from Jack Kelliher (kelliher@xmission.com)
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* Copyright (C) 2002 & pcHDTV, inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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/*
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* This driver needs two external firmware files. Please copy
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* "dvb-fe-or51132-vsb.fw" and "dvb-fe-or51132-qam.fw" to
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* /usr/lib/hotplug/firmware/ or /lib/firmware/
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* (depending on configuration of firmware hotplug).
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*/
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#define OR51132_VSB_FIRMWARE "dvb-fe-or51132-vsb.fw"
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#define OR51132_QAM_FIRMWARE "dvb-fe-or51132-qam.fw"
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <asm/byteorder.h>
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#include "dvb_frontend.h"
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#include "dvb-pll.h"
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#include "or51132.h"
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static int debug;
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#define dprintk(args...) \
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do { \
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if (debug) printk(KERN_DEBUG "or51132: " args); \
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} while (0)
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struct or51132_state
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{
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struct i2c_adapter* i2c;
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struct dvb_frontend_ops ops;
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/* Configuration settings */
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const struct or51132_config* config;
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struct dvb_frontend frontend;
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/* Demodulator private data */
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fe_modulation_t current_modulation;
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/* Tuner private data */
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u32 current_frequency;
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};
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static int i2c_writebytes (struct or51132_state* state, u8 reg, u8 *buf, int len)
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{
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int err;
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struct i2c_msg msg;
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msg.addr = reg;
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msg.flags = 0;
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msg.len = len;
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msg.buf = buf;
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if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
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printk(KERN_WARNING "or51132: i2c_writebytes error (addr %02x, err == %i)\n", reg, err);
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return -EREMOTEIO;
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}
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return 0;
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}
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static u8 i2c_readbytes (struct or51132_state* state, u8 reg, u8* buf, int len)
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{
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int err;
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struct i2c_msg msg;
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msg.addr = reg;
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msg.flags = I2C_M_RD;
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msg.len = len;
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msg.buf = buf;
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if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
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printk(KERN_WARNING "or51132: i2c_readbytes error (addr %02x, err == %i)\n", reg, err);
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return -EREMOTEIO;
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}
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return 0;
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}
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static int or51132_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
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{
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struct or51132_state* state = fe->demodulator_priv;
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static u8 run_buf[] = {0x7F,0x01};
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u8 rec_buf[8];
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u8 cmd_buf[3];
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u32 firmwareAsize, firmwareBsize;
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int i,ret;
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dprintk("Firmware is %Zd bytes\n",fw->size);
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/* Get size of firmware A and B */
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firmwareAsize = le32_to_cpu(*((u32*)fw->data));
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dprintk("FirmwareA is %i bytes\n",firmwareAsize);
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firmwareBsize = le32_to_cpu(*((u32*)(fw->data+4)));
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dprintk("FirmwareB is %i bytes\n",firmwareBsize);
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/* Upload firmware */
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if ((ret = i2c_writebytes(state,state->config->demod_address,
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&fw->data[8],firmwareAsize))) {
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printk(KERN_WARNING "or51132: load_firmware error 1\n");
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return ret;
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}
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msleep(1); /* 1ms */
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if ((ret = i2c_writebytes(state,state->config->demod_address,
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&fw->data[8+firmwareAsize],firmwareBsize))) {
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printk(KERN_WARNING "or51132: load_firmware error 2\n");
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return ret;
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}
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msleep(1); /* 1ms */
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if ((ret = i2c_writebytes(state,state->config->demod_address,
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run_buf,2))) {
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printk(KERN_WARNING "or51132: load_firmware error 3\n");
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return ret;
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}
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/* Wait at least 5 msec */
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msleep(20); /* 10ms */
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if ((ret = i2c_writebytes(state,state->config->demod_address,
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run_buf,2))) {
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printk(KERN_WARNING "or51132: load_firmware error 4\n");
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return ret;
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}
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/* 50ms for operation to begin */
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msleep(50);
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/* Read back ucode version to besure we loaded correctly and are really up and running */
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/* Get uCode version */
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cmd_buf[0] = 0x10;
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cmd_buf[1] = 0x10;
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cmd_buf[2] = 0x00;
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msleep(20); /* 20ms */
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if ((ret = i2c_writebytes(state,state->config->demod_address,
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cmd_buf,3))) {
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printk(KERN_WARNING "or51132: load_firmware error a\n");
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return ret;
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}
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cmd_buf[0] = 0x04;
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cmd_buf[1] = 0x17;
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msleep(20); /* 20ms */
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if ((ret = i2c_writebytes(state,state->config->demod_address,
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cmd_buf,2))) {
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printk(KERN_WARNING "or51132: load_firmware error b\n");
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return ret;
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}
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cmd_buf[0] = 0x00;
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cmd_buf[1] = 0x00;
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msleep(20); /* 20ms */
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if ((ret = i2c_writebytes(state,state->config->demod_address,
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cmd_buf,2))) {
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printk(KERN_WARNING "or51132: load_firmware error c\n");
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return ret;
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}
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for(i=0;i<4;i++) {
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msleep(20); /* 20ms */
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/* Once upon a time, this command might have had something
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to do with getting the firmware version, but it's
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not used anymore:
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{0x04,0x00,0x30,0x00,i+1} */
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/* Read 8 bytes, two bytes at a time */
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if ((ret = i2c_readbytes(state,state->config->demod_address,
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&rec_buf[i*2],2))) {
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printk(KERN_WARNING
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"or51132: load_firmware error d - %d\n",i);
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return ret;
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}
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}
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printk(KERN_WARNING
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"or51132: Version: %02X%02X%02X%02X-%02X%02X%02X%02X (%02X%01X-%01X-%02X%01X-%01X)\n",
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rec_buf[1],rec_buf[0],rec_buf[3],rec_buf[2],
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rec_buf[5],rec_buf[4],rec_buf[7],rec_buf[6],
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rec_buf[3],rec_buf[2]>>4,rec_buf[2]&0x0f,
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rec_buf[5],rec_buf[4]>>4,rec_buf[4]&0x0f);
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cmd_buf[0] = 0x10;
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cmd_buf[1] = 0x00;
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cmd_buf[2] = 0x00;
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msleep(20); /* 20ms */
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if ((ret = i2c_writebytes(state,state->config->demod_address,
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cmd_buf,3))) {
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printk(KERN_WARNING "or51132: load_firmware error e\n");
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return ret;
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}
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return 0;
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};
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static int or51132_init(struct dvb_frontend* fe)
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{
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return 0;
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}
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static int or51132_read_ber(struct dvb_frontend* fe, u32* ber)
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{
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*ber = 0;
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return 0;
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}
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static int or51132_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
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{
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*ucblocks = 0;
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return 0;
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}
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static int or51132_sleep(struct dvb_frontend* fe)
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{
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return 0;
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}
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static int or51132_setmode(struct dvb_frontend* fe)
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{
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struct or51132_state* state = fe->demodulator_priv;
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unsigned char cmd_buf[4];
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dprintk("setmode %d\n",(int)state->current_modulation);
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/* set operation mode in Receiver 1 register; */
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cmd_buf[0] = 0x04;
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cmd_buf[1] = 0x01;
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switch (state->current_modulation) {
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case QAM_256:
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case QAM_64:
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case QAM_AUTO:
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/* Auto-deinterleave; MPEG ser, MPEG2tr, phase noise-high*/
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cmd_buf[2] = 0x5F;
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break;
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case VSB_8:
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/* Auto CH, Auto NTSC rej, MPEGser, MPEG2tr, phase noise-high*/
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cmd_buf[2] = 0x50;
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break;
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default:
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printk("setmode:Modulation set to unsupported value\n");
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};
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cmd_buf[3] = 0x00;
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if (i2c_writebytes(state,state->config->demod_address,
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cmd_buf,3)) {
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printk(KERN_WARNING "or51132: set_mode error 1\n");
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return -1;
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}
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dprintk("or51132: set #1 to %02x\n", cmd_buf[2]);
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/* Set operation mode in Receiver 6 register */
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cmd_buf[0] = 0x1C;
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switch (state->current_modulation) {
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case QAM_AUTO:
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/* REC MODE Normal Carrier Lock */
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cmd_buf[1] = 0x00;
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/* Channel MODE Auto QAM64/256 */
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cmd_buf[2] = 0x4f;
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break;
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case QAM_256:
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/* REC MODE Normal Carrier Lock */
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cmd_buf[1] = 0x00;
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/* Channel MODE QAM256 */
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cmd_buf[2] = 0x45;
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break;
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case QAM_64:
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/* REC MODE Normal Carrier Lock */
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cmd_buf[1] = 0x00;
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/* Channel MODE QAM64 */
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cmd_buf[2] = 0x43;
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break;
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case VSB_8:
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/* REC MODE inv IF spectrum, Normal */
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cmd_buf[1] = 0x03;
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/* Channel MODE ATSC/VSB8 */
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cmd_buf[2] = 0x06;
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break;
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default:
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printk("setmode: Modulation set to unsupported value\n");
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};
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cmd_buf[3] = 0x00;
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msleep(20); /* 20ms */
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if (i2c_writebytes(state,state->config->demod_address,
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cmd_buf,3)) {
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printk(KERN_WARNING "or51132: set_mode error 2\n");
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return -1;
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}
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dprintk("or51132: set #6 to 0x%02x%02x\n", cmd_buf[1], cmd_buf[2]);
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return 0;
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}
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/* Some modulations use the same firmware. This classifies modulations
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by the firmware they use. */
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#define MOD_FWCLASS_UNKNOWN 0
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#define MOD_FWCLASS_VSB 1
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#define MOD_FWCLASS_QAM 2
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static int modulation_fw_class(fe_modulation_t modulation)
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{
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switch(modulation) {
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case VSB_8:
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return MOD_FWCLASS_VSB;
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case QAM_AUTO:
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case QAM_64:
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case QAM_256:
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return MOD_FWCLASS_QAM;
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default:
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return MOD_FWCLASS_UNKNOWN;
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}
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}
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static int or51132_set_parameters(struct dvb_frontend* fe,
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struct dvb_frontend_parameters *param)
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{
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int ret;
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u8 buf[4];
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struct or51132_state* state = fe->demodulator_priv;
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const struct firmware *fw;
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const char *fwname;
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int clock_mode;
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/* Upload new firmware only if we need a different one */
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if (modulation_fw_class(state->current_modulation) !=
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modulation_fw_class(param->u.vsb.modulation)) {
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switch(modulation_fw_class(param->u.vsb.modulation)) {
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case MOD_FWCLASS_VSB:
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dprintk("set_parameters VSB MODE\n");
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fwname = OR51132_VSB_FIRMWARE;
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/* Set non-punctured clock for VSB */
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clock_mode = 0;
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break;
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case MOD_FWCLASS_QAM:
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dprintk("set_parameters QAM MODE\n");
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fwname = OR51132_QAM_FIRMWARE;
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/* Set punctured clock for QAM */
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clock_mode = 1;
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break;
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default:
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printk("or51132: Modulation type(%d) UNSUPPORTED\n",
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param->u.vsb.modulation);
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return -1;
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}
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printk("or51132: Waiting for firmware upload(%s)...\n",
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fwname);
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ret = request_firmware(&fw, fwname, &state->i2c->dev);
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if (ret) {
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printk(KERN_WARNING "or51132: No firmware up"
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"loaded(timeout or file not found?)\n");
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return ret;
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}
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ret = or51132_load_firmware(fe, fw);
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release_firmware(fw);
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if (ret) {
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printk(KERN_WARNING "or51132: Writing firmware to "
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"device failed!\n");
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return ret;
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}
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printk("or51132: Firmware upload complete.\n");
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state->config->set_ts_params(fe, clock_mode);
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}
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/* Change only if we are actually changing the modulation */
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if (state->current_modulation != param->u.vsb.modulation) {
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state->current_modulation = param->u.vsb.modulation;
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or51132_setmode(fe);
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}
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dvb_pll_configure(state->config->pll_desc, buf,
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param->frequency, 0);
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dprintk("set_parameters tuner bytes: 0x%02x 0x%02x "
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"0x%02x 0x%02x\n",buf[0],buf[1],buf[2],buf[3]);
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if (i2c_writebytes(state, state->config->pll_address, buf, 4))
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printk(KERN_WARNING "or51132: set_parameters error "
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"writing to tuner\n");
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/* Set to current mode */
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or51132_setmode(fe);
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/* Update current frequency */
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state->current_frequency = param->frequency;
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return 0;
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}
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static int or51132_read_status(struct dvb_frontend* fe, fe_status_t* status)
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{
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struct or51132_state* state = fe->demodulator_priv;
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unsigned char rec_buf[2];
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unsigned char snd_buf[2];
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*status = 0;
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/* Receiver Status */
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snd_buf[0]=0x04;
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snd_buf[1]=0x00;
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msleep(30); /* 30ms */
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if (i2c_writebytes(state,state->config->demod_address,snd_buf,2)) {
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printk(KERN_WARNING "or51132: read_status write error\n");
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return -1;
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}
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msleep(30); /* 30ms */
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if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) {
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printk(KERN_WARNING "or51132: read_status read error\n");
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return -1;
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}
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dprintk("read_status %x %x\n",rec_buf[0],rec_buf[1]);
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if (rec_buf[1] & 0x01) { /* Receiver Lock */
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*status |= FE_HAS_SIGNAL;
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*status |= FE_HAS_CARRIER;
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*status |= FE_HAS_VITERBI;
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*status |= FE_HAS_SYNC;
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*status |= FE_HAS_LOCK;
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}
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return 0;
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}
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/* log10-1 table at .5 increments from 1 to 100.5 */
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static unsigned int i100x20log10[] = {
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0, 352, 602, 795, 954, 1088, 1204, 1306, 1397, 1480,
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1556, 1625, 1690, 1750, 1806, 1858, 1908, 1955, 2000, 2042,
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2082, 2121, 2158, 2193, 2227, 2260, 2292, 2322, 2352, 2380,
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2408, 2434, 2460, 2486, 2510, 2534, 2557, 2580, 2602, 2623,
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2644, 2664, 2684, 2704, 2723, 2742, 2760, 2778, 2795, 2813,
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2829, 2846, 2862, 2878, 2894, 2909, 2924, 2939, 2954, 2968,
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2982, 2996, 3010, 3023, 3037, 3050, 3062, 3075, 3088, 3100,
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3112, 3124, 3136, 3148, 3159, 3170, 3182, 3193, 3204, 3214,
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3225, 3236, 3246, 3256, 3266, 3276, 3286, 3296, 3306, 3316,
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3325, 3334, 3344, 3353, 3362, 3371, 3380, 3389, 3397, 3406,
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3415, 3423, 3432, 3440, 3448, 3456, 3464, 3472, 3480, 3488,
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3496, 3504, 3511, 3519, 3526, 3534, 3541, 3549, 3556, 3563,
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3570, 3577, 3584, 3591, 3598, 3605, 3612, 3619, 3625, 3632,
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3639, 3645, 3652, 3658, 3665, 3671, 3677, 3683, 3690, 3696,
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3702, 3708, 3714, 3720, 3726, 3732, 3738, 3744, 3750, 3755,
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3761, 3767, 3772, 3778, 3784, 3789, 3795, 3800, 3806, 3811,
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3816, 3822, 3827, 3832, 3838, 3843, 3848, 3853, 3858, 3863,
|
|
3868, 3874, 3879, 3884, 3888, 3893, 3898, 3903, 3908, 3913,
|
|
3918, 3922, 3927, 3932, 3936, 3941, 3946, 3950, 3955, 3960,
|
|
3964, 3969, 3973, 3978, 3982, 3986, 3991, 3995, 4000, 4004,
|
|
};
|
|
|
|
static unsigned int denom[] = {1,1,100,1000,10000,100000,1000000,10000000,100000000};
|
|
|
|
static unsigned int i20Log10(unsigned short val)
|
|
{
|
|
unsigned int rntval = 100;
|
|
unsigned int tmp = val;
|
|
unsigned int exp = 1;
|
|
|
|
while(tmp > 100) {tmp /= 100; exp++;}
|
|
|
|
val = (2 * val)/denom[exp];
|
|
if (exp > 1) rntval = 2000*exp;
|
|
|
|
rntval += i100x20log10[val];
|
|
return rntval;
|
|
}
|
|
|
|
static int or51132_read_signal_strength(struct dvb_frontend* fe, u16* strength)
|
|
{
|
|
struct or51132_state* state = fe->demodulator_priv;
|
|
unsigned char rec_buf[2];
|
|
unsigned char snd_buf[2];
|
|
u8 rcvr_stat;
|
|
u16 snr_equ;
|
|
u32 signal_strength;
|
|
int usK;
|
|
|
|
snd_buf[0]=0x04;
|
|
snd_buf[1]=0x02; /* SNR after Equalizer */
|
|
msleep(30); /* 30ms */
|
|
if (i2c_writebytes(state,state->config->demod_address,snd_buf,2)) {
|
|
printk(KERN_WARNING "or51132: read_status write error\n");
|
|
return -1;
|
|
}
|
|
msleep(30); /* 30ms */
|
|
if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) {
|
|
printk(KERN_WARNING "or51132: read_status read error\n");
|
|
return -1;
|
|
}
|
|
snr_equ = rec_buf[0] | (rec_buf[1] << 8);
|
|
dprintk("read_signal_strength snr_equ %x %x (%i)\n",rec_buf[0],rec_buf[1],snr_equ);
|
|
|
|
/* Receiver Status */
|
|
snd_buf[0]=0x04;
|
|
snd_buf[1]=0x00;
|
|
msleep(30); /* 30ms */
|
|
if (i2c_writebytes(state,state->config->demod_address,snd_buf,2)) {
|
|
printk(KERN_WARNING "or51132: read_signal_strength read_status write error\n");
|
|
return -1;
|
|
}
|
|
msleep(30); /* 30ms */
|
|
if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) {
|
|
printk(KERN_WARNING "or51132: read_signal_strength read_status read error\n");
|
|
return -1;
|
|
}
|
|
dprintk("read_signal_strength read_status %x %x\n",rec_buf[0],rec_buf[1]);
|
|
rcvr_stat = rec_buf[1];
|
|
usK = (rcvr_stat & 0x10) ? 3 : 0;
|
|
|
|
/* The value reported back from the frontend will be FFFF=100% 0000=0% */
|
|
signal_strength = (((8952 - i20Log10(snr_equ) - usK*100)/3+5)*65535)/1000;
|
|
if (signal_strength > 0xffff)
|
|
*strength = 0xffff;
|
|
else
|
|
*strength = signal_strength;
|
|
dprintk("read_signal_strength %i\n",*strength);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int or51132_read_snr(struct dvb_frontend* fe, u16* snr)
|
|
{
|
|
struct or51132_state* state = fe->demodulator_priv;
|
|
unsigned char rec_buf[2];
|
|
unsigned char snd_buf[2];
|
|
u16 snr_equ;
|
|
|
|
snd_buf[0]=0x04;
|
|
snd_buf[1]=0x02; /* SNR after Equalizer */
|
|
msleep(30); /* 30ms */
|
|
if (i2c_writebytes(state,state->config->demod_address,snd_buf,2)) {
|
|
printk(KERN_WARNING "or51132: read_snr write error\n");
|
|
return -1;
|
|
}
|
|
msleep(30); /* 30ms */
|
|
if (i2c_readbytes(state,state->config->demod_address,rec_buf,2)) {
|
|
printk(KERN_WARNING "or51132: read_snr dvr read error\n");
|
|
return -1;
|
|
}
|
|
snr_equ = rec_buf[0] | (rec_buf[1] << 8);
|
|
dprintk("read_snr snr_equ %x %x (%i)\n",rec_buf[0],rec_buf[1],snr_equ);
|
|
|
|
*snr = 0xFFFF - snr_equ;
|
|
dprintk("read_snr %i\n",*snr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int or51132_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
|
|
{
|
|
fe_tune_settings->min_delay_ms = 500;
|
|
fe_tune_settings->step_size = 0;
|
|
fe_tune_settings->max_drift = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void or51132_release(struct dvb_frontend* fe)
|
|
{
|
|
struct or51132_state* state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
static struct dvb_frontend_ops or51132_ops;
|
|
|
|
struct dvb_frontend* or51132_attach(const struct or51132_config* config,
|
|
struct i2c_adapter* i2c)
|
|
{
|
|
struct or51132_state* state = NULL;
|
|
|
|
/* Allocate memory for the internal state */
|
|
state = kmalloc(sizeof(struct or51132_state), GFP_KERNEL);
|
|
if (state == NULL)
|
|
goto error;
|
|
|
|
/* Setup the state */
|
|
state->config = config;
|
|
state->i2c = i2c;
|
|
memcpy(&state->ops, &or51132_ops, sizeof(struct dvb_frontend_ops));
|
|
state->current_frequency = -1;
|
|
state->current_modulation = -1;
|
|
|
|
/* Create dvb_frontend */
|
|
state->frontend.ops = &state->ops;
|
|
state->frontend.demodulator_priv = state;
|
|
return &state->frontend;
|
|
|
|
error:
|
|
kfree(state);
|
|
return NULL;
|
|
}
|
|
|
|
static struct dvb_frontend_ops or51132_ops = {
|
|
|
|
.info = {
|
|
.name = "Oren OR51132 VSB/QAM Frontend",
|
|
.type = FE_ATSC,
|
|
.frequency_min = 44000000,
|
|
.frequency_max = 958000000,
|
|
.frequency_stepsize = 166666,
|
|
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
|
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
|
|
FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
|
|
FE_CAN_8VSB
|
|
},
|
|
|
|
.release = or51132_release,
|
|
|
|
.init = or51132_init,
|
|
.sleep = or51132_sleep,
|
|
|
|
.set_frontend = or51132_set_parameters,
|
|
.get_tune_settings = or51132_get_tune_settings,
|
|
|
|
.read_status = or51132_read_status,
|
|
.read_ber = or51132_read_ber,
|
|
.read_signal_strength = or51132_read_signal_strength,
|
|
.read_snr = or51132_read_snr,
|
|
.read_ucblocks = or51132_read_ucblocks,
|
|
};
|
|
|
|
module_param(debug, int, 0644);
|
|
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
|
|
|
|
MODULE_DESCRIPTION("OR51132 ATSC [pcHDTV HD-3000] (8VSB & ITU J83 AnnexB FEC QAM64/256) Demodulator Driver");
|
|
MODULE_AUTHOR("Kirk Lapray");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
EXPORT_SYMBOL(or51132_attach);
|
|
|
|
/*
|
|
* Local variables:
|
|
* c-basic-offset: 8
|
|
* End:
|
|
*/
|