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e0a8e0d90a
Use of APG for handling PAGE_USER.
All pages PP exec bits are set to either 000 or 011, which means
respectively RW for Supervisor and no access for User, or RO for
Supervisor and no access for user.
Then we use the APG to say whether accesses are according to
Page rules or "all Supervisor" rules (Access to all)
Therefore, we define 2 APG groups corresponding to _PAGE_USER.
Mx_AP are initialised as follows:
GP0 => No user => 01 (all accesses performed according
to page definition)
GP1 => User => 00 (all accesses performed as supervisor
according to page definition)
This removes the special 8xx handling in pte_update()
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
341 lines
11 KiB
C
341 lines
11 KiB
C
#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
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#define _ASM_POWERPC_PGTABLE_PPC32_H
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#include <asm-generic/pgtable-nopmd.h>
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <linux/threads.h>
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#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
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extern unsigned long ioremap_bot;
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#ifdef CONFIG_44x
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extern int icache_44x_need_flush;
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#endif
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#endif /* __ASSEMBLY__ */
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/*
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* The normal case is that PTEs are 32-bits and we have a 1-page
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* 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
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*
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* For any >32-bit physical address platform, we can use the following
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* two level page table layout where the pgdir is 8KB and the MS 13 bits
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* are an index to the second level table. The combined pgdir/pmd first
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* level has 2048 entries and the second level has 512 64-bit PTE entries.
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* -Matt
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*/
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/* PGDIR_SHIFT determines what a top-level page table entry can map */
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#define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* entries per page directory level: our page-table tree is two-level, so
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* we don't really have any PMD directory.
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*/
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#ifndef __ASSEMBLY__
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#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
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#endif /* __ASSEMBLY__ */
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#define PTRS_PER_PTE (1 << PTE_SHIFT)
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#define PTRS_PER_PMD 1
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#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
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#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0UL
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
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(unsigned long long)pte_val(e))
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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/*
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* This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
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* value (for now) on others, from where we can start layout kernel
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* virtual space that goes below PKMAP and FIXMAP
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*/
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#ifdef CONFIG_HIGHMEM
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#define KVIRT_TOP PKMAP_BASE
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#else
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#define KVIRT_TOP (0xfe000000UL) /* for now, could be FIXMAP_BASE ? */
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#endif
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/*
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* ioremap_bot starts at that address. Early ioremaps move down from there,
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* until mem_init() at which point this becomes the top of the vmalloc
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* and ioremap space
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*/
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#ifdef CONFIG_NOT_COHERENT_CACHE
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#define IOREMAP_TOP ((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
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#else
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#define IOREMAP_TOP KVIRT_TOP
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#endif
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/*
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* Just any arbitrary offset to the start of the vmalloc VM area: the
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* current 16MB value just means that there will be a 64MB "hole" after the
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* physical memory until the kernel virtual memory starts. That means that
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* any out-of-bounds memory accesses will hopefully be caught.
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* The vmalloc() routines leaves a hole of 4kB between each vmalloced
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* area for the same reason. ;)
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*
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* We no longer map larger than phys RAM with the BATs so we don't have
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* to worry about the VMALLOC_OFFSET causing problems. We do have to worry
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* about clashes between our early calls to ioremap() that start growing down
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* from ioremap_base being run into the VM area allocations (growing upwards
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* from VMALLOC_START). For this reason we have ioremap_bot to check when
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* we actually run into our mappings setup in the early boot with the VM
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* system. This really does become a problem for machines with good amounts
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* of RAM. -- Cort
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*/
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#define VMALLOC_OFFSET (0x1000000) /* 16M */
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#ifdef PPC_PIN_SIZE
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#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
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#else
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#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
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#endif
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#define VMALLOC_END ioremap_bot
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/*
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* Bits in a linux-style PTE. These match the bits in the
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* (hardware-defined) PowerPC PTE as closely as possible.
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*/
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#if defined(CONFIG_40x)
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#include <asm/pte-40x.h>
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#elif defined(CONFIG_44x)
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#include <asm/pte-44x.h>
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#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
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#include <asm/pte-book3e.h>
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#elif defined(CONFIG_FSL_BOOKE)
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#include <asm/pte-fsl-booke.h>
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#elif defined(CONFIG_8xx)
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#include <asm/pte-8xx.h>
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#else /* CONFIG_6xx */
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#include <asm/pte-hash32.h>
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#endif
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/* And here we include common definitions */
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#include <asm/pte-common.h>
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#ifndef __ASSEMBLY__
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#define pte_clear(mm, addr, ptep) \
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do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
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#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
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#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
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/*
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* When flushing the tlb entry for a page, we also need to flush the hash
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* table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
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*/
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extern int flush_hash_pages(unsigned context, unsigned long va,
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unsigned long pmdval, int count);
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/* Add an HPTE to the hash table */
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extern void add_hash_page(unsigned context, unsigned long va,
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unsigned long pmdval);
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/* Flush an entry from the TLB/hash table */
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extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
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unsigned long address);
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/*
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* PTE updates. This function is called whenever an existing
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* valid PTE is updated. This does -not- include set_pte_at()
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* which nowadays only sets a new PTE.
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*
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* Depending on the type of MMU, we may need to use atomic updates
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* and the PTE may be either 32 or 64 bit wide. In the later case,
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* when using atomic updates, only the low part of the PTE is
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* accessed atomically.
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*
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* In addition, on 44x, we also maintain a global flag indicating
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* that an executable user mapping was modified, which is needed
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* to properly flush the virtually tagged instruction cache of
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* those implementations.
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*/
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#ifndef CONFIG_PTE_64BIT
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static inline unsigned long pte_update(pte_t *p,
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unsigned long clr,
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unsigned long set)
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{
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#ifdef PTE_ATOMIC_UPDATES
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unsigned long old, tmp;
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__asm__ __volatile__("\
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1: lwarx %0,0,%3\n\
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andc %1,%0,%4\n\
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or %1,%1,%5\n"
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PPC405_ERR77(0,%3)
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" stwcx. %1,0,%3\n\
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bne- 1b"
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: "=&r" (old), "=&r" (tmp), "=m" (*p)
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: "r" (p), "r" (clr), "r" (set), "m" (*p)
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: "cc" );
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#else /* PTE_ATOMIC_UPDATES */
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unsigned long old = pte_val(*p);
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*p = __pte((old & ~clr) | set);
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#endif /* !PTE_ATOMIC_UPDATES */
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#ifdef CONFIG_44x
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if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
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icache_44x_need_flush = 1;
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#endif
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return old;
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}
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#else /* CONFIG_PTE_64BIT */
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static inline unsigned long long pte_update(pte_t *p,
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unsigned long clr,
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unsigned long set)
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{
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#ifdef PTE_ATOMIC_UPDATES
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unsigned long long old;
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unsigned long tmp;
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__asm__ __volatile__("\
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1: lwarx %L0,0,%4\n\
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lwzx %0,0,%3\n\
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andc %1,%L0,%5\n\
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or %1,%1,%6\n"
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PPC405_ERR77(0,%3)
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" stwcx. %1,0,%4\n\
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bne- 1b"
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: "=&r" (old), "=&r" (tmp), "=m" (*p)
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: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
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: "cc" );
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#else /* PTE_ATOMIC_UPDATES */
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unsigned long long old = pte_val(*p);
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*p = __pte((old & ~(unsigned long long)clr) | set);
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#endif /* !PTE_ATOMIC_UPDATES */
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#ifdef CONFIG_44x
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if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
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icache_44x_need_flush = 1;
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#endif
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return old;
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}
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#endif /* CONFIG_PTE_64BIT */
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/*
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* 2.6 calls this without flushing the TLB entry; this is wrong
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* for our hash-based implementation, we fix that up here.
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*/
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
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{
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unsigned long old;
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old = pte_update(ptep, _PAGE_ACCESSED, 0);
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#if _PAGE_HASHPTE != 0
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if (old & _PAGE_HASHPTE) {
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unsigned long ptephys = __pa(ptep) & PAGE_MASK;
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flush_hash_pages(context, addr, ptephys, 1);
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}
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#endif
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return (old & _PAGE_ACCESSED) != 0;
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}
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#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
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__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
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}
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), _PAGE_RO);
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}
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static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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ptep_set_wrprotect(mm, addr, ptep);
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}
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static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
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{
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unsigned long set = pte_val(entry) &
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(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
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unsigned long clr = ~pte_val(entry) & _PAGE_RO;
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pte_update(ptep, clr, set);
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}
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#define __HAVE_ARCH_PTE_SAME
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#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
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/*
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* Note that on Book E processors, the pmd contains the kernel virtual
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* (lowmem) address of the pte page. The physical address is less useful
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* because everything runs with translation enabled (even the TLB miss
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* handler). On everything else the pmd contains the physical address
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* of the pte page. -- paulus
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*/
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#ifndef CONFIG_BOOKE
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#define pmd_page_vaddr(pmd) \
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((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
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#define pmd_page(pmd) \
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pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
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#else
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#define pmd_page_vaddr(pmd) \
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((unsigned long) (pmd_val(pmd) & PAGE_MASK))
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#define pmd_page(pmd) \
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pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
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#endif
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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/* to find an entry in a page-table-directory */
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#define pgd_index(address) ((address) >> PGDIR_SHIFT)
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#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
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/* Find an entry in the third-level page table.. */
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#define pte_index(address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir, addr) \
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((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
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#define pte_offset_map(dir, addr) \
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((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
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#define pte_unmap(pte) kunmap_atomic(pte)
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/*
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* Encode and decode a swap entry.
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* Note that the bits we use in a PTE for representing a swap entry
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* must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used).
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* -- paulus
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*/
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#define __swp_type(entry) ((entry).val & 0x1f)
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#define __swp_offset(entry) ((entry).val >> 5)
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#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
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#ifndef CONFIG_PPC_4K_PAGES
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void pgtable_cache_init(void);
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#else
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do { } while (0)
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#endif
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extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
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pmd_t **pmdp);
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
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