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https://github.com/torvalds/linux
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8690bbcf3b
Introduce a generic way to query whether the data cache is virtually
aliased on all architectures. Its purpose is to ensure that subsystems
which are incompatible with virtually aliased data caches (e.g. FS_DAX)
can reliably query this.
For data cache aliasing, there are three scenarios dependending on the
architecture. Here is a breakdown based on my understanding:
A) The data cache is always aliasing:
* arc
* csky
* m68k (note: shared memory mappings are incoherent ? SHMLBA is missing there.)
* sh
* parisc
B) The data cache aliasing is statically known or depends on querying CPU
state at runtime:
* arm (cache_is_vivt() || cache_is_vipt_aliasing())
* mips (cpu_has_dc_aliases)
* nios2 (NIOS2_DCACHE_SIZE > PAGE_SIZE)
* sparc32 (vac_cache_size > PAGE_SIZE)
* sparc64 (L1DCACHE_SIZE > PAGE_SIZE)
* xtensa (DCACHE_WAY_SIZE > PAGE_SIZE)
C) The data cache is never aliasing:
* alpha
* arm64 (aarch64)
* hexagon
* loongarch (but with incoherent write buffers, which are disabled since
commit d23b7795 ("LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE"))
* microblaze
* openrisc
* powerpc
* riscv
* s390
* um
* x86
Require architectures in A) and B) to select ARCH_HAS_CPU_CACHE_ALIASING and
implement "cpu_dcache_is_aliasing()".
Architectures in C) don't select ARCH_HAS_CPU_CACHE_ALIASING, and thus
cpu_dcache_is_aliasing() simply evaluates to "false".
Note that this leaves "cpu_icache_is_aliasing()" to be implemented as future
work. This would be useful to gate features like XIP on architectures
which have aliasing CPU dcache-icache but not CPU dcache-dcache.
Use "cpu_dcache" and "cpu_cache" rather than just "dcache" and "cache"
to clarify that we really mean "CPU data cache" and "CPU cache" to
eliminate any possible confusion with VFS "dentry cache" and "page
cache".
Link: https://lore.kernel.org/lkml/20030910210416.GA24258@mail.jlokier.co.uk/
Link: https://lkml.kernel.org/r/20240215144633.96437-9-mathieu.desnoyers@efficios.com
Fixes: d92576f116 ("dax: does not work correctly with virtual aliasing caches")
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Alasdair Kergon <agk@redhat.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Dave Chinner <david@fromorbit.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: kernel test robot <lkp@intel.com>
Cc: Michael Sclafani <dm-devel@lists.linux.dev>
Cc: Mike Snitzer <snitzer@kernel.org>
Cc: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
132 lines
2.7 KiB
Plaintext
132 lines
2.7 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config M68K
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bool
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default y
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select ARCH_32BIT_OFF_T
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select ARCH_HAS_CPU_CACHE_ALIASING
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select ARCH_HAS_BINFMT_FLAT
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select ARCH_HAS_CPU_FINALIZE_INIT if MMU
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select ARCH_HAS_CURRENT_STACK_POINTER
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select ARCH_HAS_DMA_PREP_COHERENT if M68K_NONCOHERENT_DMA && !COLDFIRE
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE if M68K_NONCOHERENT_DMA
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select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
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select ARCH_MIGHT_HAVE_PC_PARPORT if ISA
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select ARCH_NO_PREEMPT if !COLDFIRE
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select ARCH_USE_MEMTEST if MMU_MOTOROLA
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select ARCH_WANT_IPC_PARSE_VERSION
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select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
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select DMA_DIRECT_REMAP if M68K_NONCOHERENT_DMA && !COLDFIRE
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select GENERIC_ATOMIC64
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select GENERIC_CPU_DEVICES
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select GENERIC_IOMAP
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select GENERIC_IRQ_SHOW
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select GENERIC_LIB_ASHLDI3
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select GENERIC_LIB_ASHRDI3
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select GENERIC_LIB_LSHRDI3
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select HAS_IOPORT if PCI || ISA || ATARI_ROM_ISA
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select HAVE_ARCH_SECCOMP
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select HAVE_ARCH_SECCOMP_FILTER
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select HAVE_ASM_MODVERSIONS
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select HAVE_DEBUG_BUGVERBOSE
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select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED
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select HAVE_MOD_ARCH_SPECIFIC
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select HAVE_UID16
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select MMU_GATHER_NO_RANGE if MMU
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select MODULES_USE_ELF_REL
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select MODULES_USE_ELF_RELA
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select NO_DMA if !MMU && !COLDFIRE
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select OLD_SIGACTION
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select OLD_SIGSUSPEND3
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select UACCESS_MEMCPY if !MMU
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select ZONE_DMA
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config CPU_BIG_ENDIAN
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def_bool y
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config ARCH_HAS_ILOG2_U32
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bool
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config ARCH_HAS_ILOG2_U64
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bool
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config GENERIC_HWEIGHT
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bool
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default y
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config GENERIC_CALIBRATE_DELAY
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bool
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default y
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config GENERIC_CSUM
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bool
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config TIME_LOW_RES
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bool
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default y
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config NO_IOPORT_MAP
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def_bool y
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config HZ
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int
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default 1000 if CLEOPATRA
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default 100
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config PGTABLE_LEVELS
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default 2 if SUN3 || COLDFIRE
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default 3
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config MMU
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bool "MMU-based Paged Memory Management Support"
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default y
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help
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Select if you want MMU-based virtualised addressing space
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support by paged memory management. If unsure, say 'Y'.
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config MMU_MOTOROLA
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bool
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config MMU_COLDFIRE
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bool
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config MMU_SUN3
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bool
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depends on MMU && !MMU_MOTOROLA && !MMU_COLDFIRE
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config ARCH_SUPPORTS_KEXEC
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def_bool M68KCLASSIC && MMU
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config BOOTINFO_PROC
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bool "Export bootinfo in procfs"
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depends on KEXEC && M68KCLASSIC
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help
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Say Y to export the bootinfo used to boot the kernel in a
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"bootinfo" file in procfs. This is useful with kexec.
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menu "Platform setup"
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source "arch/m68k/Kconfig.cpu"
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source "arch/m68k/Kconfig.machine"
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source "arch/m68k/Kconfig.bus"
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endmenu
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menu "Kernel Features"
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endmenu
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if !MMU
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menu "Power management options"
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config PM
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bool "Power Management support"
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help
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Support processor power management modes
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endmenu
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endif
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source "arch/m68k/Kconfig.devices"
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