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https://github.com/torvalds/linux
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fb1c8f93d8
This patch (written by me and also containing many suggestions of Arjan van de Ven) does a major cleanup of the spinlock code. It does the following things: - consolidates and enhances the spinlock/rwlock debugging code - simplifies the asm/spinlock.h files - encapsulates the raw spinlock type and moves generic spinlock features (such as ->break_lock) into the generic code. - cleans up the spinlock code hierarchy to get rid of the spaghetti. Most notably there's now only a single variant of the debugging code, located in lib/spinlock_debug.c. (previously we had one SMP debugging variant per architecture, plus a separate generic one for UP builds) Also, i've enhanced the rwlock debugging facility, it will now track write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too. All locks have lockup detection now, which will work for both soft and hard spin/rwlock lockups. The arch-level include files now only contain the minimally necessary subset of the spinlock code - all the rest that can be generalized now lives in the generic headers: include/asm-i386/spinlock_types.h | 16 include/asm-x86_64/spinlock_types.h | 16 I have also split up the various spinlock variants into separate files, making it easier to see which does what. The new layout is: SMP | UP ----------------------------|----------------------------------- asm/spinlock_types_smp.h | linux/spinlock_types_up.h linux/spinlock_types.h | linux/spinlock_types.h asm/spinlock_smp.h | linux/spinlock_up.h linux/spinlock_api_smp.h | linux/spinlock_api_up.h linux/spinlock.h | linux/spinlock.h /* * here's the role of the various spinlock/rwlock related include files: * * on SMP builds: * * asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the * initializers * * linux/spinlock_types.h: * defines the generic type and initializers * * asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel * implementations, mostly inline assembly code * * (also included on UP-debug builds:) * * linux/spinlock_api_smp.h: * contains the prototypes for the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. * * on UP builds: * * linux/spinlock_type_up.h: * contains the generic, simplified UP spinlock type. * (which is an empty structure on non-debug builds) * * linux/spinlock_types.h: * defines the generic type and initializers * * linux/spinlock_up.h: * contains the __raw_spin_*()/etc. version of UP * builds. (which are NOPs on non-debug, non-preempt * builds) * * (included on UP-non-debug builds:) * * linux/spinlock_api_up.h: * builds the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. */ All SMP and UP architectures are converted by this patch. arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should be mostly fine. From: Grant Grundler <grundler@parisc-linux.org> Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU). Builds 32-bit SMP kernel (not booted or tested). I did not try to build non-SMP kernels. That should be trivial to fix up later if necessary. I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids some ugly nesting of linux/*.h and asm/*.h files. Those particular locks are well tested and contained entirely inside arch specific code. I do NOT expect any new issues to arise with them. If someone does ever need to use debug/metrics with them, then they will need to unravel this hairball between spinlocks, atomic ops, and bit ops that exist only because parisc has exactly one atomic instruction: LDCW (load and clear word). From: "Luck, Tony" <tony.luck@intel.com> ia64 fix Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjanv@infradead.org> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Cc: Matthew Wilcox <willy@debian.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se> Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
164 lines
3.1 KiB
C
164 lines
3.1 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/system.h>
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/*
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* Simple spin lock operations.
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*
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* (the type definitions are in asm/raw_spinlock_types.h)
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*/
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"b 1f # __raw_spin_lock\n\
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2: lwzx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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bne+ 2b\n\
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1: lwarx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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bne- 2b\n"
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PPC405_ERR77(0,%1)
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" stwcx. %2,0,%1\n\
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bne- 2b\n\
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isync"
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: "=&r"(tmp)
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: "r"(&lock->lock), "r"(1)
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: "cr0", "memory");
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__("eieio # __raw_spin_unlock": : :"memory");
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lock->lock = 0;
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}
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#define __raw_spin_trylock(l) (!test_and_set_bit(0,&(l)->lock))
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
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#define __raw_write_can_lock(rw) (!(rw)->lock)
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static __inline__ int __raw_read_trylock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"2: lwarx %0,0,%1 # read_trylock\n\
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addic. %0,%0,1\n\
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ble- 1f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 2b\n\
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isync\n\
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1:"
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: "=&r"(tmp)
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: "r"(&rw->lock)
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: "cr0", "memory");
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return tmp > 0;
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}
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static __inline__ void __raw_read_lock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"b 2f # read_lock\n\
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1: lwzx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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blt+ 1b\n\
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2: lwarx %0,0,%1\n\
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addic. %0,%0,1\n\
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ble- 1b\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 2b\n\
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isync"
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: "=&r"(tmp)
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: "r"(&rw->lock)
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: "cr0", "memory");
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}
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static __inline__ void __raw_read_unlock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"eieio # read_unlock\n\
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1: lwarx %0,0,%1\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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: "=&r"(tmp)
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: "r"(&rw->lock)
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: "cr0", "memory");
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}
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static __inline__ int __raw_write_trylock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"2: lwarx %0,0,%1 # write_trylock\n\
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cmpwi 0,%0,0\n\
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bne- 1f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %2,0,%1\n\
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bne- 2b\n\
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isync\n\
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1:"
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: "=&r"(tmp)
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: "r"(&rw->lock), "r"(-1)
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: "cr0", "memory");
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return tmp == 0;
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}
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static __inline__ void __raw_write_lock(raw_rwlock_t *rw)
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{
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signed int tmp;
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__asm__ __volatile__(
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"b 2f # write_lock\n\
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1: lwzx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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bne+ 1b\n\
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2: lwarx %0,0,%1\n\
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cmpwi 0,%0,0\n\
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bne- 1b\n"
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PPC405_ERR77(0,%1)
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" stwcx. %2,0,%1\n\
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bne- 2b\n\
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isync"
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: "=&r"(tmp)
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: "r"(&rw->lock), "r"(-1)
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: "cr0", "memory");
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}
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static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
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{
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__asm__ __volatile__("eieio # write_unlock": : :"memory");
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rw->lock = 0;
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}
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#endif /* __ASM_SPINLOCK_H */
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