linux/arch/mips/cavium-octeon/executive
David Daney b8db85b5b5 MIPS: Octeon: Update L2 Cache code for CN63XX
The CN63XX has a different L2 cache architecture.  Update the helper
functions to reflect this.

Some joining of split lines was also done to improve readability, as
well as reformatting of comments.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1663/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:35 +01:00
..
cvmx-bootmem.c MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1) 2010-02-27 12:53:43 +01:00
cvmx-helper-errata.c MIPS: Export erratum function needed by octeon-ethernet driver. 2009-06-17 11:06:29 +01:00
cvmx-helper-jtag.c MIPS: Add Cavium OCTEON PCI support. 2009-06-17 11:06:25 +01:00
cvmx-l2c.c MIPS: Octeon: Update L2 Cache code for CN63XX 2010-10-29 19:08:35 +01:00
cvmx-sysinfo.c MIPS: Nuke trailing blank lines 2010-02-27 12:53:14 +01:00
Makefile MIPS: Octeon: Determine if helper needs to be built 2010-10-04 18:33:55 +01:00
octeon-model.c