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The DLL(Delay Line) is newly added to assist in sampling read data. The DLL provides the ability to programmatically select a quantized delay (in fractions of the clock period) regardless of on-chip variations such as process, voltage and temperature (PVT). This patch adds a user interface to set slave delay line via device tree. It's usually used in high speed mode like mmc DDR mode when the signal quality is not good caused by board design, e.g. the signal path is too long. User can manually set delay line to find a suitable data sampling window for card to work properly. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
38 lines
1.2 KiB
Plaintext
38 lines
1.2 KiB
Plaintext
* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
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The Enhanced Secure Digital Host Controller on Freescale i.MX family
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provides an interface for MMC, SD, and SDIO types of memory cards.
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This file documents differences between the core properties described
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by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
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Required properties:
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- compatible : Should be "fsl,<chip>-esdhc"
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Optional properties:
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- fsl,cd-controller : Indicate to use controller internal card detection
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- fsl,wp-controller : Indicate to use controller internal write protection
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- fsl,delay-line : Specify the number of delay cells for override mode.
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This is used to set the clock delay for DLL(Delay Line) on override mode
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to select a proper data sampling window in case the clock quality is not good
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due to signal path is too long on the board. Please refer to eSDHC/uSDHC
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chapter, DLL (Delay Line) section in RM for details.
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Examples:
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esdhc@70004000 {
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compatible = "fsl,imx51-esdhc";
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reg = <0x70004000 0x4000>;
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interrupts = <1>;
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fsl,cd-controller;
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fsl,wp-controller;
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};
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esdhc@70008000 {
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compatible = "fsl,imx51-esdhc";
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reg = <0x70008000 0x4000>;
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interrupts = <2>;
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cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
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wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
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};
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