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82a682676c
This conversion will allow to keep 32 bits addresses for the internal registers whereas the memory of the system will be 64 bits. Later it will also ease the move of the mvebu-mbus driver to the device tree support. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
163 lines
3.2 KiB
Plaintext
163 lines
3.2 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada XP SoC that are not
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* common to all Armada SoCs.
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*/
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/include/ "armada-370-xp.dtsi"
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/ {
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model = "Marvell Armada XP family SoC";
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compatible = "marvell,armadaxp", "marvell,armada-370-xp";
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soc {
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L2: l2-cache {
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compatible = "marvell,aurora-system-cache";
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reg = <0x08000 0x1000>;
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cache-id-part = <0x100>;
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wt-override;
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};
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mpic: interrupt-controller@20000 {
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reg = <0x20a00 0x2d0>,
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<0x21070 0x58>;
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};
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armada-370-xp-pmsu@22000 {
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compatible = "marvell,armada-370-xp-pmsu";
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reg = <0x22100 0x430>,
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<0x20800 0x20>;
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};
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serial@12200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12200 0x100>;
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reg-shift = <2>;
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interrupts = <43>;
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reg-io-width = <1>;
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status = "disabled";
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};
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serial@12300 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12300 0x100>;
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reg-shift = <2>;
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interrupts = <44>;
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reg-io-width = <1>;
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status = "disabled";
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};
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timer@20300 {
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marvell,timer-25Mhz;
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};
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coreclk: mvebu-sar@18230 {
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compatible = "marvell,armada-xp-core-clock";
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reg = <0x18230 0x08>;
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#clock-cells = <1>;
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};
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cpuclk: clock-complex@18700 {
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#clock-cells = <1>;
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compatible = "marvell,armada-xp-cpu-clock";
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reg = <0x18700 0xA0>;
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clocks = <&coreclk 1>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,armada-xp-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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system-controller@18200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x500>;
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};
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ethernet@30000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x30000 0x2500>;
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interrupts = <12>;
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clocks = <&gateclk 2>;
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status = "disabled";
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};
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xor@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor10 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor@f0900 {
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compatible = "marvell,orion-xor";
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reg = <0xF0900 0x100
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0xF0B00 0x100>;
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clocks = <&gateclk 28>;
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status = "okay";
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xor00 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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usb@50000 {
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clocks = <&gateclk 18>;
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};
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usb@51000 {
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clocks = <&gateclk 19>;
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};
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usb@52000 {
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compatible = "marvell,orion-ehci";
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reg = <0x52000 0x500>;
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interrupts = <47>;
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clocks = <&gateclk 20>;
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status = "disabled";
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};
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thermal@182b0 {
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compatible = "marvell,armadaxp-thermal";
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reg = <0x182b0 0x4
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0x184d0 0x4>;
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status = "okay";
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};
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};
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};
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