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c461731836
Multiple Loongson-3A chips can be interconnected with HT0-bus. This is a CC-NUMA system that every chip (node) has its own local memory and cache coherency is maintained by hardware. The 64-bit physical memory address format is as follows: 0x-0000-YZZZ-ZZZZ-ZZZZ The high 16 bits should be 0, which means the real physical address supported by Loongson-3 is 48-bit. The "Y" bits is the base address of each node, which can be also considered as the node-id. The "Z" bits is the address offset within a node, which means every node has a 44 bits address space. Macros XPHYSADDR and MAX_PHYSMEM_BITS are modified unconditionally, because many other MIPS CPUs have also extended their address spaces. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7187/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
18 lines
447 B
C
18 lines
447 B
C
#ifndef _MIPS_SPARSEMEM_H
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#define _MIPS_SPARSEMEM_H
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#ifdef CONFIG_SPARSEMEM
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/*
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* SECTION_SIZE_BITS 2^N: how big each section will be
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* MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
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*/
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#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && defined(CONFIG_PAGE_SIZE_64KB)
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# define SECTION_SIZE_BITS 29
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#else
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# define SECTION_SIZE_BITS 28
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#endif
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#define MAX_PHYSMEM_BITS 48
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#endif /* CONFIG_SPARSEMEM */
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#endif /* _MIPS_SPARSEMEM_H */
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