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https://github.com/torvalds/linux
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f821e349cf
Remove the last address definitions relative to the IPSBAR peripheral region for the ColdFire 527x family. This involved cleaning up some magic numbers used in the code part, and making them proper register definitions in the 527x specific header. This is part of the process of cleaning up the ColdFire register definitions to make them consistently use absolute addresses for the primary registers. This will reduce the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
99 lines
2.5 KiB
C
99 lines
2.5 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/527x/config.c
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*
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* Sub-architcture dependent initialization code for the Freescale
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* 5270/5271 CPUs.
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*
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* Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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/***************************************************************************/
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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static void __init m527x_qspi_init(void)
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{
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#if defined(CONFIG_M5271)
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u16 par;
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/* setup QSPS pins for QSPI with gpio CS control */
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writeb(0x1f, MCFGPIO_PAR_QSPI);
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/* and CS2 & CS3 as gpio */
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par = readw(MCFGPIO_PAR_TIMER);
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par &= 0x3f3f;
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writew(par, MCFGPIO_PAR_TIMER);
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#elif defined(CONFIG_M5275)
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/* setup QSPS pins for QSPI with gpio CS control */
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writew(0x003e, MCFGPIO_PAR_QSPI);
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#endif
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}
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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/***************************************************************************/
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static void __init m527x_uarts_init(void)
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{
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u16 sepmask;
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/*
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* External Pin Mask Setting & Enable External Pin for Interface
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*/
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sepmask = readw(MCFGPIO_PAR_UART);
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sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
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writew(sepmask, MCFGPIO_PAR_UART);
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}
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/***************************************************************************/
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static void __init m527x_fec_init(void)
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{
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u16 par;
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u8 v;
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/* Set multi-function pins to ethernet mode for fec0 */
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#if defined(CONFIG_M5271)
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v = readb(MCFGPIO_PAR_FECI2C);
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writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
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#else
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par = readw(MCFGPIO_PAR_FECI2C);
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writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
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v = readb(MCFGPIO_PAR_FEC0HL);
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writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
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/* Set multi-function pins to ethernet mode for fec1 */
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par = readw(MCFGPIO_PAR_FECI2C);
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writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
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v = readb(MCFGPIO_PAR_FEC1HL);
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writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
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#endif
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_sched_init = hw_timer_init;
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m527x_uarts_init();
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m527x_fec_init();
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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m527x_qspi_init();
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#endif
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}
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/***************************************************************************/
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