mirror of
https://github.com/torvalds/linux
synced 2024-11-05 18:23:50 +00:00
a26be149fa
This time with:
* Generic page-table framework for ARM IOMMUs using the LPAE page-table
format, ARM-SMMU and Renesas IPMMU make use of it already.
* Break out of the IO virtual address allocator from the Intel IOMMU so
that it can be used by other DMA-API implementations too. The first
user will be the ARM64 common DMA-API implementation for IOMMUs
* Device tree support for Renesas IPMMU
* Various fixes and cleanups all over the place
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJU3MJOAAoJECvwRC2XARrjopUP+wachFx8vb00M4hlnlwL6FCn
DyIFkA1n4wL0muPhjcBI+LViEXrSxjr2TYoJEaBg+fiByWWQ1Hefg+KPz331Lo1D
+uo7WiOa1AB3pfkQiUN9IN6xx+o6ivhb3UQPiL4FHjggB/qz+KVxMM9nx0j8o0fQ
D9q6HLFiOIsFkra3xZaSuDGvYUBpcwyfn8FP1HVfvLlg1uxIGDcUJX3qU5UBpj9q
al/lPZ4A7rp+JLApV6WyouPiyVOZKikb5x920KeRNBem7a9fNBdgf+x7QbKpNXa1
5MaT5MarwGe8lJE4wtjOqRtsllhia+A1rg/6JbROPrlGetRFiuIh2sCKLvwOCko/
IjBHSutpaRT1lFoAG0TAnXQlvHRG/58XxOlP3eF613X/p8/cezuUaTyTIwZam9X3
j2GWwbUcBiHTxlu7bQDPz6a7cTf4w6wEALzYl18QrAFv+2LqlCfOo/LSlpStmjrF
kRN8DYaohlTULvmFneSr8rfGsnp5yPgIPvdmqiSwTz/Ih7kYPgfLy6+v6IAHUqZj
0n9oGs8eMqVvSzM2qqmyA9WGuQZRyhNjj4iDwn/he5YMw2kqxUQYGMpLnSu0Oi48
n4PqodtVol64jKLwaHZwyU8u71iyjUC5K9TDot/I2wlSRcTELJhxGh6c1sfDLyrO
u/htIszgKCgFvVrQoEZB
=dwrA
-----END PGP SIGNATURE-----
Merge tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel:
"This time with:
- Generic page-table framework for ARM IOMMUs using the LPAE
page-table format, ARM-SMMU and Renesas IPMMU make use of it
already.
- Break out the IO virtual address allocator from the Intel IOMMU so
that it can be used by other DMA-API implementations too. The
first user will be the ARM64 common DMA-API implementation for
IOMMUs
- Device tree support for Renesas IPMMU
- Various fixes and cleanups all over the place"
* tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (36 commits)
iommu/amd: Convert non-returned local variable to boolean when relevant
iommu: Update my email address
iommu/amd: Use wait_event in put_pasid_state_wait
iommu/amd: Fix amd_iommu_free_device()
iommu/arm-smmu: Avoid build warning
iommu/fsl: Various cleanups
iommu/fsl: Use %pa to print phys_addr_t
iommu/omap: Print phys_addr_t using %pa
iommu: Make more drivers depend on COMPILE_TEST
iommu/ipmmu-vmsa: Fix IOMMU lookup when multiple IOMMUs are registered
iommu: Disable on !MMU builds
iommu/fsl: Remove unused fsl_of_pamu_ids[]
iommu/fsl: Fix section mismatch
iommu/ipmmu-vmsa: Use the ARM LPAE page table allocator
iommu: Fix trace_map() to report original iova and original size
iommu/arm-smmu: add support for iova_to_phys through ATS1PR
iopoll: Introduce memory-mapped IO polling macros
iommu/arm-smmu: don't touch the secure STLBIALL register
iommu/arm-smmu: make use of generic LPAE allocator
iommu: io-pgtable-arm: add non-secure quirk
...
92 lines
3.3 KiB
C
92 lines
3.3 KiB
C
/*
|
|
* Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
|
|
* Author: Joerg Roedel <jroedel@suse.de>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License version 2 as published
|
|
* by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
*/
|
|
|
|
#ifndef _ASM_X86_AMD_IOMMU_PROTO_H
|
|
#define _ASM_X86_AMD_IOMMU_PROTO_H
|
|
|
|
#include "amd_iommu_types.h"
|
|
|
|
extern int amd_iommu_init_dma_ops(void);
|
|
extern int amd_iommu_init_passthrough(void);
|
|
extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
|
|
extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
|
|
extern void amd_iommu_apply_erratum_63(u16 devid);
|
|
extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
|
|
extern int amd_iommu_init_devices(void);
|
|
extern void amd_iommu_uninit_devices(void);
|
|
extern void amd_iommu_init_notifier(void);
|
|
extern void amd_iommu_init_api(void);
|
|
|
|
/* Needed for interrupt remapping */
|
|
extern int amd_iommu_prepare(void);
|
|
extern int amd_iommu_enable(void);
|
|
extern void amd_iommu_disable(void);
|
|
extern int amd_iommu_reenable(int);
|
|
extern int amd_iommu_enable_faulting(void);
|
|
|
|
/* IOMMUv2 specific functions */
|
|
struct iommu_domain;
|
|
|
|
extern bool amd_iommu_v2_supported(void);
|
|
extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
|
|
extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
|
|
extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
|
|
extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
|
|
extern int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
|
|
u64 address);
|
|
extern int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid);
|
|
extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
|
|
unsigned long cr3);
|
|
extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid);
|
|
extern struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev);
|
|
|
|
/* IOMMU Performance Counter functions */
|
|
extern bool amd_iommu_pc_supported(void);
|
|
extern u8 amd_iommu_pc_get_max_banks(u16 devid);
|
|
extern u8 amd_iommu_pc_get_max_counters(u16 devid);
|
|
extern int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
|
|
u64 *value, bool is_write);
|
|
|
|
#define PPR_SUCCESS 0x0
|
|
#define PPR_INVALID 0x1
|
|
#define PPR_FAILURE 0xf
|
|
|
|
extern int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
|
|
int status, int tag);
|
|
|
|
#ifndef CONFIG_AMD_IOMMU_STATS
|
|
|
|
static inline void amd_iommu_stats_init(void) { }
|
|
|
|
#endif /* !CONFIG_AMD_IOMMU_STATS */
|
|
|
|
static inline bool is_rd890_iommu(struct pci_dev *pdev)
|
|
{
|
|
return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
|
|
(pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
|
|
}
|
|
|
|
static inline bool iommu_feature(struct amd_iommu *iommu, u64 f)
|
|
{
|
|
if (!(iommu->cap & (1 << IOMMU_CAP_EFR)))
|
|
return false;
|
|
|
|
return !!(iommu->features & f);
|
|
}
|
|
|
|
#endif /* _ASM_X86_AMD_IOMMU_PROTO_H */
|