Aaron Brice 77da3da0b2 mmc: sdhci-esdhc-imx: Correct two register accesses ... - The DMA error interrupt bit is in a different position as compared to the sdhci standard. This is accounted for in many cases, but not handled in the case of clearing the INT_STATUS register by writing a 1 to that location. - The HOST_CONTROL register is very different as compared to the sdhci standard. This is accounted for in the write case, but not when read back out (which it is in the sdhci code). Signed-off-by: Dave Russell <david.russell@datasoft.com> Signed-off-by: Aaron Brice <aaron.brice@datasoft.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>		2016-10-13 08:58:03 +02:00
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card	mmc: core: Annotate cmd_hdr as __le32	2016-10-10 14:14:49 +02:00
core	mmc: core: changes frequency to hs_max_dtr when selecting hs400es	2016-10-10 14:01:15 +02:00
host	mmc: sdhci-esdhc-imx: Correct two register accesses	2016-10-13 08:58:03 +02:00
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