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761bbcb74e
Use INCR8 mode for system bus interface of the USB controller on MPC512x. This is a work-around for the AHB bus lock up problem observed on MPC512x when there is heavy simultaneous PATA write or network (FEC) activity. See also "12.4 The USB controller can issue transactions that lock up the AHB bus under certain conditions" in MPC5121e (M36P) Errata. Signed-off-by: Anatolij Gustschin <agust@denx.de> Tested-by: Matthias Fuchs <matthias.fuchs@esd.ue> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
52 lines
2 KiB
C
52 lines
2 KiB
C
/* Copyright (C) 2005-2010 Freescale Semiconductor, Inc.
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* Copyright (c) 2005 MontaVista Software
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _EHCI_FSL_H
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#define _EHCI_FSL_H
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/* offsets for the non-ehci registers in the FSL SOC USB controller */
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#define FSL_SOC_USB_SBUSCFG 0x90
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#define SBUSCFG_INCR8 0x02 /* INCR8, specified */
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#define FSL_SOC_USB_ULPIVP 0x170
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#define FSL_SOC_USB_PORTSC1 0x184
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#define PORT_PTS_MSK (3<<30)
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#define PORT_PTS_UTMI (0<<30)
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#define PORT_PTS_ULPI (2<<30)
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#define PORT_PTS_SERIAL (3<<30)
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#define PORT_PTS_PTW (1<<28)
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#define FSL_SOC_USB_PORTSC2 0x188
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#define FSL_SOC_USB_USBMODE 0x1a8
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#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
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#define USBMODE_CM_HOST (3 << 0) /* controller mode: host */
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#define USBMODE_ES (1 << 2) /* (Big) Endian Select */
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#define FSL_SOC_USB_USBGENCTRL 0x200
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#define USBGENCTRL_PPP (1 << 3)
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#define USBGENCTRL_PFP (1 << 2)
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#define FSL_SOC_USB_ISIPHYCTRL 0x204
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#define ISIPHYCTRL_PXE (1)
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#define ISIPHYCTRL_PHYE (1 << 4)
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#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
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#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
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#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
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#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
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#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
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#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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#define SNOOP_SIZE_2GB 0x1e
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#endif /* _EHCI_FSL_H */
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