mirror of
https://github.com/torvalds/linux
synced 2024-11-05 18:23:50 +00:00
fb24ea52f7
mmiowb() is now implied by spin_unlock() on architectures that require it, so there is no reason to call it from driver code. This patch was generated using coccinelle: @mmiowb@ @@ - mmiowb(); and invoked as: $ for d in drivers include/linux/qed sound; do \ spatch --include-headers --sp-file mmiowb.cocci --dir $d --in-place; done NOTE: mmiowb() has only ever guaranteed ordering in conjunction with spin_unlock(). However, pairing each mmiowb() removal in this patch with the corresponding call to spin_unlock() is not at all trivial, so there is a small chance that this change may regress any drivers incorrectly relying on mmiowb() to order MMIO writes between CPUs using lock-free synchronisation. If you've ended up bisecting to this commit, you can reintroduce the mmiowb() calls using wmb() instead, which should restore the old behaviour on all architectures other than some esoteric ia64 systems. Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
233 lines
6.2 KiB
C
233 lines
6.2 KiB
C
/*
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* TXx9 ACLC AC97 driver
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*
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* Copyright (C) 2009 Atsushi Nemoto
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*
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* Based on RBTX49xx patch from CELF patch archive.
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* (C) Copyright TOSHIBA CORPORATION 2004-2006
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gfp.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/soc.h>
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#include "txx9aclc.h"
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#define AC97_DIR \
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(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
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#define AC97_RATES \
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SNDRV_PCM_RATE_8000_48000
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#ifdef __BIG_ENDIAN
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#define AC97_FMTS SNDRV_PCM_FMTBIT_S16_BE
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#else
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#define AC97_FMTS SNDRV_PCM_FMTBIT_S16_LE
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#endif
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static DECLARE_WAIT_QUEUE_HEAD(ac97_waitq);
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/* REVISIT: How to find txx9aclc_drvdata from snd_ac97? */
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static struct txx9aclc_plat_drvdata *txx9aclc_drvdata;
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static int txx9aclc_regready(struct txx9aclc_plat_drvdata *drvdata)
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{
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return __raw_readl(drvdata->base + ACINTSTS) & ACINT_REGACCRDY;
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}
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/* AC97 controller reads codec register */
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static unsigned short txx9aclc_ac97_read(struct snd_ac97 *ac97,
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unsigned short reg)
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{
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struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
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void __iomem *base = drvdata->base;
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u32 dat;
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if (!(__raw_readl(base + ACINTSTS) & ACINT_CODECRDY(ac97->num)))
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return 0xffff;
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reg |= ac97->num << 7;
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dat = (reg << ACREGACC_REG_SHIFT) | ACREGACC_READ;
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__raw_writel(dat, base + ACREGACC);
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__raw_writel(ACINT_REGACCRDY, base + ACINTEN);
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if (!wait_event_timeout(ac97_waitq, txx9aclc_regready(txx9aclc_drvdata), HZ)) {
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__raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
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printk(KERN_ERR "ac97 read timeout (reg %#x)\n", reg);
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dat = 0xffff;
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goto done;
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}
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dat = __raw_readl(base + ACREGACC);
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if (((dat >> ACREGACC_REG_SHIFT) & 0xff) != reg) {
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printk(KERN_ERR "reg mismatch %x with %x\n",
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dat, reg);
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dat = 0xffff;
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goto done;
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}
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dat = (dat >> ACREGACC_DAT_SHIFT) & 0xffff;
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done:
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__raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
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return dat;
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}
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/* AC97 controller writes to codec register */
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static void txx9aclc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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unsigned short val)
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{
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struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
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void __iomem *base = drvdata->base;
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__raw_writel(((reg | (ac97->num << 7)) << ACREGACC_REG_SHIFT) |
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(val << ACREGACC_DAT_SHIFT),
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base + ACREGACC);
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__raw_writel(ACINT_REGACCRDY, base + ACINTEN);
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if (!wait_event_timeout(ac97_waitq, txx9aclc_regready(txx9aclc_drvdata), HZ)) {
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printk(KERN_ERR
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"ac97 write timeout (reg %#x)\n", reg);
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}
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__raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
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}
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static void txx9aclc_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
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void __iomem *base = drvdata->base;
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u32 ready = ACINT_CODECRDY(ac97->num) | ACINT_REGACCRDY;
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__raw_writel(ACCTL_ENLINK, base + ACCTLDIS);
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udelay(1);
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__raw_writel(ACCTL_ENLINK, base + ACCTLEN);
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/* wait for primary codec ready status */
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__raw_writel(ready, base + ACINTEN);
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if (!wait_event_timeout(ac97_waitq,
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(__raw_readl(base + ACINTSTS) & ready) == ready,
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HZ)) {
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dev_err(&ac97->dev, "primary codec is not ready "
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"(status %#x)\n",
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__raw_readl(base + ACINTSTS));
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}
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__raw_writel(ACINT_REGACCRDY, base + ACINTSTS);
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__raw_writel(ready, base + ACINTDIS);
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}
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/* AC97 controller operations */
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static struct snd_ac97_bus_ops txx9aclc_ac97_ops = {
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.read = txx9aclc_ac97_read,
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.write = txx9aclc_ac97_write,
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.reset = txx9aclc_ac97_cold_reset,
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};
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static irqreturn_t txx9aclc_ac97_irq(int irq, void *dev_id)
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{
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struct txx9aclc_plat_drvdata *drvdata = dev_id;
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void __iomem *base = drvdata->base;
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__raw_writel(__raw_readl(base + ACINTMSTS), base + ACINTDIS);
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wake_up(&ac97_waitq);
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return IRQ_HANDLED;
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}
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static int txx9aclc_ac97_probe(struct snd_soc_dai *dai)
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{
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txx9aclc_drvdata = snd_soc_dai_get_drvdata(dai);
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return 0;
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}
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static int txx9aclc_ac97_remove(struct snd_soc_dai *dai)
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{
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struct txx9aclc_plat_drvdata *drvdata = snd_soc_dai_get_drvdata(dai);
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/* disable AC-link */
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__raw_writel(ACCTL_ENLINK, drvdata->base + ACCTLDIS);
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txx9aclc_drvdata = NULL;
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return 0;
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}
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static struct snd_soc_dai_driver txx9aclc_ac97_dai = {
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.bus_control = true,
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.probe = txx9aclc_ac97_probe,
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.remove = txx9aclc_ac97_remove,
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.playback = {
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.rates = AC97_RATES,
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.formats = AC97_FMTS,
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.channels_min = 2,
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.channels_max = 2,
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},
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.capture = {
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.rates = AC97_RATES,
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.formats = AC97_FMTS,
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.channels_min = 2,
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.channels_max = 2,
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},
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};
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static const struct snd_soc_component_driver txx9aclc_ac97_component = {
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.name = "txx9aclc-ac97",
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};
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static int txx9aclc_ac97_dev_probe(struct platform_device *pdev)
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{
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struct txx9aclc_plat_drvdata *drvdata;
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struct resource *r;
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int err;
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int irq;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
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if (!drvdata)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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drvdata->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(drvdata->base))
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return PTR_ERR(drvdata->base);
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platform_set_drvdata(pdev, drvdata);
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drvdata->physbase = r->start;
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if (sizeof(drvdata->physbase) > sizeof(r->start) &&
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r->start >= TXX9_DIRECTMAP_BASE &&
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r->start < TXX9_DIRECTMAP_BASE + 0x400000)
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drvdata->physbase |= 0xf00000000ull;
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err = devm_request_irq(&pdev->dev, irq, txx9aclc_ac97_irq,
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0, dev_name(&pdev->dev), drvdata);
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if (err < 0)
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return err;
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err = snd_soc_set_ac97_ops(&txx9aclc_ac97_ops);
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if (err < 0)
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return err;
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return devm_snd_soc_register_component(&pdev->dev, &txx9aclc_ac97_component,
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&txx9aclc_ac97_dai, 1);
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}
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static int txx9aclc_ac97_dev_remove(struct platform_device *pdev)
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{
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snd_soc_set_ac97_ops(NULL);
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return 0;
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}
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static struct platform_driver txx9aclc_ac97_driver = {
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.probe = txx9aclc_ac97_dev_probe,
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.remove = txx9aclc_ac97_dev_remove,
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.driver = {
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.name = "txx9aclc-ac97",
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},
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};
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module_platform_driver(txx9aclc_ac97_driver);
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MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
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MODULE_DESCRIPTION("TXx9 ACLC AC97 driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:txx9aclc-ac97");
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