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f83ccb9358
A large part of the arm-soc patches are nowadays DT changes, adding support for new SoCs, boards and devices without changing kernel source. The plan is still to move the devicetree files out of the kernel tree and reduce the amount of churn going on here, but we keep finding reasons to delay doing that. Changes are really all over the place, with little sticking out particularly. We have contributions from a total of 116 people in this branch. Unfortunately, the size of this branch also causes a significant number of conflicts at the moment, typically when subsystem maintainers merge patches that change the driver at the same time as the dts files. In most cases this could be avoided because the dts changes are supposed to be compatible in both ways, and we are asking everyone to send ARM dts changes through our tree only. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUz/11WCrR//JCVInAQIIyRAA0DjdNNQ/A4G2i1nZCiTFH6a4oZy4JarN ATVPkW/V8avhh+yVNe5FWA44Xe6CDC5TXwMaIsbK+w3Iclj3fplh/MsBkQ9ZT9Sl LAjJoOjuYucCeDy0WLVioRKZ4PJEDoCu/oZTauIMnmWCOCRxLYpOM3FkAT9oN/Ti lswpTSLiV1/U3ZSI4M3qn+Sx1VJL8c/hAIWbvf5if2diYkWPk3VOSKyxmD9zLWdD Iqtb79J+ETVeOIM4sHnx79cG4ZCdpOfRAl7qx6hkJu0YATXESxWhpXVE2McTJuzM qHKsRRNSfsfSWPeF4angll9o06X/qgdT6C4P2dfH49lGeG7llOttw3OaCx3hWCTe U5bt26qtbwG2ZbzocaqvideP+rbpQrCH2vdO1embPv5Lu6peMoBWjxy6twSVXJBG LIymJ0IbiGYxL7BReGqRXt6ehy0BDWBeTSTdsGqgEl2TnxHuS/kgGfJc4D5riiEk aRPVq10p/k+yo4BZtq2GqXIOG6cqkIQ5lhl5Tg9+MfUlquAONqJP70FgRJDBIw9L 9uJp71bgSsA6eYg2tXoqJtpdjKplDWavgtACzIkFg2qFLyYmKvx+F0AXbeTIsrri /mIchTyG+dgiIjWvj/Xsf7jhrdzRcl3uKsJwFmk927pIsh24HV8T+LKgHrf+sVcO qEsEnKGYA6s= =zl/N -----END PGP SIGNATURE----- Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree changes from Arnd Bergmann: "A large part of the arm-soc patches are nowadays DT changes, adding support for new SoCs, boards and devices without changing kernel source. The plan is still to move the devicetree files out of the kernel tree and reduce the amount of churn going on here, but we keep finding reasons to delay doing that. Changes are really all over the place, with little sticking out particularly. We have contributions from a total of 116 people in this branch. Unfortunately, the size of this branch also causes a significant number of conflicts at the moment, typically when subsystem maintainers merge patches that change the driver at the same time as the dts files. In most cases this could be avoided because the dts changes are supposed to be compatible in both ways, and we are asking everyone to send ARM dts changes through our tree only" * tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits) dts: stmmac: Document the clocks property in the stmmac base document dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. ARM: STi: stih41x: Add support for the FSM Serial Flash Controller ARM: STi: stih416: Add support for the FSM Serial Flash Controller ARM: tegra: fix Dalmore pinctrl configuration ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND ARM: dts: Build all keystone dt blobs ARM: dts: keystone: Fix control register range for clktsip ARM: dts: keystone: Fix domain register range for clkfftc1 ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap ARM: dts: bcm21664: Add device tree files. ARM: DT: bcm21664: Device tree bindings ARM: efm32: properly namespace i2c location property ARM: efm32: fix unit address part in USART2 device nodes' names ARM: mvebu: Enable NAND controller in Armada 385-DB ARM: mvebu: Add support for NAND controller in Armada 38x SoC ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs ...
737 lines
18 KiB
Plaintext
737 lines
18 KiB
Plaintext
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "skeleton.dtsi"
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#include "imx53-pinfunc.h"
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#include <dt-bindings/clock/imx5-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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mmc0 = &esdhc1;
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mmc1 = &esdhc2;
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mmc2 = &esdhc3;
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mmc3 = &esdhc4;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &cspi;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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};
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};
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&ipu_di0>, <&ipu_di1>;
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};
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tzic: tz-interrupt-controller@0fffc000 {
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compatible = "fsl,imx53-tzic", "fsl,tzic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x0fffc000 0x4000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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clock-frequency = <22579200>;
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};
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ckih2 {
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compatible = "fsl,imx-ckih2", "fixed-clock";
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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clock-frequency = <24000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&tzic>;
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ranges;
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sata: sata@10000000 {
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compatible = "fsl,imx53-ahci";
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reg = <0x10000000 0x1000>;
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interrupts = <28>;
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clocks = <&clks IMX5_CLK_SATA_GATE>,
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<&clks IMX5_CLK_SATA_REF>,
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<&clks IMX5_CLK_AHB>;
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clock-names = "sata_gate", "sata_ref", "ahb";
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status = "disabled";
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};
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ipu: ipu@18000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ipu";
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reg = <0x18000000 0x080000000>;
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interrupts = <11 10>;
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clocks = <&clks IMX5_CLK_IPU_GATE>,
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<&clks IMX5_CLK_IPU_DI0_GATE>,
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<&clks IMX5_CLK_IPU_DI1_GATE>;
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clock-names = "bus", "di0", "di1";
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resets = <&src 2>;
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ipu_di0: port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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ipu_di0_disp0: endpoint@0 {
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reg = <0>;
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};
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ipu_di0_lvds0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds0_in>;
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};
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};
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ipu_di1: port@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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ipu_di1_disp1: endpoint@0 {
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reg = <0>;
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};
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ipu_di1_lvds1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds1_in>;
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};
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ipu_di1_tve: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&tve_in>;
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};
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};
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};
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aips@50000000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x10000000>;
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ranges;
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spba@50000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x40000>;
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ranges;
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esdhc1: esdhc@50004000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50004000 0x4000>;
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interrupts = <1>;
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clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC1_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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esdhc2: esdhc@50008000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50008000 0x4000>;
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interrupts = <2>;
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clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC2_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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uart3: serial@5000c000 {
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compatible = "fsl,imx53-uart", "fsl,imx21-uart";
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reg = <0x5000c000 0x4000>;
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interrupts = <33>;
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clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
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<&clks IMX5_CLK_UART3_PER_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi1: ecspi@50010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
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reg = <0x50010000 0x4000>;
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interrupts = <36>;
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clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
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<&clks IMX5_CLK_ECSPI1_PER_GATE>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ssi2: ssi@50014000 {
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compatible = "fsl,imx53-ssi",
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"fsl,imx51-ssi",
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"fsl,imx21-ssi";
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reg = <0x50014000 0x4000>;
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interrupts = <30>;
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clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
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dmas = <&sdma 24 1 0>,
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<&sdma 25 1 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <15>;
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fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
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status = "disabled";
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};
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esdhc3: esdhc@50020000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50020000 0x4000>;
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interrupts = <3>;
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clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC3_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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esdhc4: esdhc@50024000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50024000 0x4000>;
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interrupts = <4>;
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clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC4_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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};
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usbphy0: usbphy@0 {
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compatible = "usb-nop-xceiv";
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clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
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clock-names = "main_clk";
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status = "okay";
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};
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usbphy1: usbphy@1 {
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compatible = "usb-nop-xceiv";
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clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
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clock-names = "main_clk";
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status = "okay";
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};
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usbotg: usb@53f80000 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80000 0x0200>;
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interrupts = <18>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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fsl,usbmisc = <&usbmisc 0>;
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fsl,usbphy = <&usbphy0>;
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status = "disabled";
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};
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usbh1: usb@53f80200 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80200 0x0200>;
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interrupts = <14>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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fsl,usbmisc = <&usbmisc 1>;
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fsl,usbphy = <&usbphy1>;
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status = "disabled";
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};
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usbh2: usb@53f80400 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80400 0x0200>;
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interrupts = <16>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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fsl,usbmisc = <&usbmisc 2>;
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status = "disabled";
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};
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usbh3: usb@53f80600 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80600 0x0200>;
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interrupts = <17>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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fsl,usbmisc = <&usbmisc 3>;
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status = "disabled";
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};
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usbmisc: usbmisc@53f80800 {
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#index-cells = <1>;
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compatible = "fsl,imx53-usbmisc";
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reg = <0x53f80800 0x200>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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};
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gpio1: gpio@53f84000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f84000 0x4000>;
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interrupts = <50 51>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@53f88000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f88000 0x4000>;
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interrupts = <52 53>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@53f8c000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f8c000 0x4000>;
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interrupts = <54 55>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@53f90000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f90000 0x4000>;
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interrupts = <56 57>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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kpp: kpp@53f94000 {
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compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
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reg = <0x53f94000 0x4000>;
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interrupts = <60>;
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clocks = <&clks IMX5_CLK_DUMMY>;
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status = "disabled";
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};
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wdog1: wdog@53f98000 {
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compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
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reg = <0x53f98000 0x4000>;
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interrupts = <58>;
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clocks = <&clks IMX5_CLK_DUMMY>;
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};
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wdog2: wdog@53f9c000 {
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compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
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reg = <0x53f9c000 0x4000>;
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interrupts = <59>;
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clocks = <&clks IMX5_CLK_DUMMY>;
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status = "disabled";
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};
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gpt: timer@53fa0000 {
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compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
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reg = <0x53fa0000 0x4000>;
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interrupts = <39>;
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clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
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<&clks IMX5_CLK_GPT_HF_GATE>;
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clock-names = "ipg", "per";
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};
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iomuxc: iomuxc@53fa8000 {
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compatible = "fsl,imx53-iomuxc";
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reg = <0x53fa8000 0x4000>;
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};
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gpr: iomuxc-gpr@53fa8000 {
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compatible = "fsl,imx53-iomuxc-gpr", "syscon";
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reg = <0x53fa8000 0xc>;
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};
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ldb: ldb@53fa8008 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ldb";
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reg = <0x53fa8008 0x4>;
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gpr = <&gpr>;
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clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
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<&clks IMX5_CLK_LDB_DI1_SEL>,
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<&clks IMX5_CLK_IPU_DI0_SEL>,
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<&clks IMX5_CLK_IPU_DI1_SEL>,
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<&clks IMX5_CLK_LDB_DI0_GATE>,
|
|
<&clks IMX5_CLK_LDB_DI1_GATE>;
|
|
clock-names = "di0_pll", "di1_pll",
|
|
"di0_sel", "di1_sel",
|
|
"di0", "di1";
|
|
status = "disabled";
|
|
|
|
lvds-channel@0 {
|
|
reg = <0>;
|
|
status = "disabled";
|
|
|
|
port {
|
|
lvds0_in: endpoint {
|
|
remote-endpoint = <&ipu_di0_lvds0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
lvds-channel@1 {
|
|
reg = <1>;
|
|
status = "disabled";
|
|
|
|
port {
|
|
lvds1_in: endpoint {
|
|
remote-endpoint = <&ipu_di0_lvds0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
pwm1: pwm@53fb4000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
|
reg = <0x53fb4000 0x4000>;
|
|
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
|
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
|
clock-names = "ipg", "per";
|
|
interrupts = <61>;
|
|
};
|
|
|
|
pwm2: pwm@53fb8000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
|
reg = <0x53fb8000 0x4000>;
|
|
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
|
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
|
clock-names = "ipg", "per";
|
|
interrupts = <94>;
|
|
};
|
|
|
|
uart1: serial@53fbc000 {
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
|
reg = <0x53fbc000 0x4000>;
|
|
interrupts = <31>;
|
|
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
|
<&clks IMX5_CLK_UART1_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@53fc0000 {
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
|
reg = <0x53fc0000 0x4000>;
|
|
interrupts = <32>;
|
|
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
|
<&clks IMX5_CLK_UART2_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@53fc8000 {
|
|
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
|
reg = <0x53fc8000 0x4000>;
|
|
interrupts = <82>;
|
|
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
|
|
<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
can2: can@53fcc000 {
|
|
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
|
reg = <0x53fcc000 0x4000>;
|
|
interrupts = <83>;
|
|
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
|
|
<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
src: src@53fd0000 {
|
|
compatible = "fsl,imx53-src", "fsl,imx51-src";
|
|
reg = <0x53fd0000 0x4000>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
clks: ccm@53fd4000{
|
|
compatible = "fsl,imx53-ccm";
|
|
reg = <0x53fd4000 0x4000>;
|
|
interrupts = <0 71 0x04 0 72 0x04>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gpio5: gpio@53fdc000 {
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53fdc000 0x4000>;
|
|
interrupts = <103 104>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio@53fe0000 {
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53fe0000 0x4000>;
|
|
interrupts = <105 106>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio7: gpio@53fe4000 {
|
|
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
|
reg = <0x53fe4000 0x4000>;
|
|
interrupts = <107 108>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
i2c3: i2c@53fec000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
|
reg = <0x53fec000 0x4000>;
|
|
interrupts = <64>;
|
|
clocks = <&clks IMX5_CLK_I2C3_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@53ff0000 {
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
|
reg = <0x53ff0000 0x4000>;
|
|
interrupts = <13>;
|
|
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
|
|
<&clks IMX5_CLK_UART4_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
aips@60000000 { /* AIPS2 */
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x60000000 0x10000000>;
|
|
ranges;
|
|
|
|
iim: iim@63f98000 {
|
|
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
|
|
reg = <0x63f98000 0x4000>;
|
|
interrupts = <69>;
|
|
clocks = <&clks IMX5_CLK_IIM_GATE>;
|
|
};
|
|
|
|
uart5: serial@63f90000 {
|
|
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
|
reg = <0x63f90000 0x4000>;
|
|
interrupts = <86>;
|
|
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
|
|
<&clks IMX5_CLK_UART5_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
owire: owire@63fa4000 {
|
|
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
|
|
reg = <0x63fa4000 0x4000>;
|
|
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi2: ecspi@63fac000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x63fac000 0x4000>;
|
|
interrupts = <37>;
|
|
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
|
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdma: sdma@63fb0000 {
|
|
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
|
reg = <0x63fb0000 0x4000>;
|
|
interrupts = <6>;
|
|
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
|
<&clks IMX5_CLK_SDMA_GATE>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
|
};
|
|
|
|
cspi: cspi@63fc0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
|
|
reg = <0x63fc0000 0x4000>;
|
|
interrupts = <38>;
|
|
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
|
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@63fc4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
|
reg = <0x63fc4000 0x4000>;
|
|
interrupts = <63>;
|
|
clocks = <&clks IMX5_CLK_I2C2_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@63fc8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
|
reg = <0x63fc8000 0x4000>;
|
|
interrupts = <62>;
|
|
clocks = <&clks IMX5_CLK_I2C1_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi1: ssi@63fcc000 {
|
|
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
|
|
"fsl,imx21-ssi";
|
|
reg = <0x63fcc000 0x4000>;
|
|
interrupts = <29>;
|
|
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
|
|
dmas = <&sdma 28 0 0>,
|
|
<&sdma 29 0 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
|
status = "disabled";
|
|
};
|
|
|
|
audmux: audmux@63fd0000 {
|
|
compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
|
|
reg = <0x63fd0000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
nfc: nand@63fdb000 {
|
|
compatible = "fsl,imx53-nand";
|
|
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
|
|
interrupts = <8>;
|
|
clocks = <&clks IMX5_CLK_NFC_GATE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi3: ssi@63fe8000 {
|
|
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
|
|
"fsl,imx21-ssi";
|
|
reg = <0x63fe8000 0x4000>;
|
|
interrupts = <96>;
|
|
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
|
|
dmas = <&sdma 46 0 0>,
|
|
<&sdma 47 0 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
|
|
status = "disabled";
|
|
};
|
|
|
|
fec: ethernet@63fec000 {
|
|
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
|
reg = <0x63fec000 0x4000>;
|
|
interrupts = <87>;
|
|
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
|
<&clks IMX5_CLK_FEC_GATE>,
|
|
<&clks IMX5_CLK_FEC_GATE>;
|
|
clock-names = "ipg", "ahb", "ptp";
|
|
status = "disabled";
|
|
};
|
|
|
|
tve: tve@63ff0000 {
|
|
compatible = "fsl,imx53-tve";
|
|
reg = <0x63ff0000 0x1000>;
|
|
interrupts = <92>;
|
|
clocks = <&clks IMX5_CLK_TVE_GATE>,
|
|
<&clks IMX5_CLK_IPU_DI1_SEL>;
|
|
clock-names = "tve", "di_sel";
|
|
status = "disabled";
|
|
|
|
port {
|
|
tve_in: endpoint {
|
|
remote-endpoint = <&ipu_di1_tve>;
|
|
};
|
|
};
|
|
};
|
|
|
|
vpu: vpu@63ff4000 {
|
|
compatible = "fsl,imx53-vpu";
|
|
reg = <0x63ff4000 0x1000>;
|
|
interrupts = <9>;
|
|
clocks = <&clks IMX5_CLK_VPU_GATE>,
|
|
<&clks IMX5_CLK_VPU_GATE>;
|
|
clock-names = "per", "ahb";
|
|
iram = <&ocram>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
ocram: sram@f8000000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0xf8000000 0x20000>;
|
|
clocks = <&clks IMX5_CLK_OCRAM>;
|
|
};
|
|
};
|
|
};
|