Andreas Schwab 732e8e4130 RISC-V: properly determine hardware caps ... On the Hifive-U platform, cpu 0 is a masked cpu with less capabilities than the other cpus. Ignore it for the purpose of determining the hardware capabilities of the system. Signed-off-by: Andreas Schwab <schwab@suse.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-10-31 12:13:43 -07:00
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configs	irqchip: add a SiFive PLIC driver	2018-08-13 08:31:32 -07:00
include	RISC-V: SMP cleanup and new features	2018-10-22 17:41:43 -07:00
kernel	RISC-V: properly determine hardware caps	2018-10-31 12:13:43 -07:00
lib	RISC-V: Build tishift only on 64-bit	2018-10-22 17:02:55 -07:00
mm	RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap	2018-10-22 17:02:56 -07:00
Kconfig	RISC-V: Fix some RV32 bugs and build failures	2018-10-22 17:39:08 -07:00
Kconfig.debug	RISC-V: Cosmetic menuconfig changes	2018-10-22 17:38:20 -07:00
Makefile	riscv: Add support to no-FPU systems	2018-10-22 17:38:26 -07:00