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728390fce4
Add the compatible "intel,socfpga-agilex-hsotg" to the DWC2 implementation, because the Agilex DWC2 implementation does not support clock gating. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> |
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| .. | ||
| bindings | ||
| changesets.rst | ||
| dynamic-resolution-notes.rst | ||
| index.rst | ||
| kernel-api.rst | ||
| of_unittest.rst | ||
| overlay-notes.rst | ||
| usage-model.rst | ||