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![Paul Mackerras](/assets/img/avatar_default.png)
This fixes a race which can result in the same virtual IRQ number being assigned to two different MSI interrupts. The most visible consequence of that is usually a warning and stack trace from the sysfs code about an attempt to create a duplicate entry in sysfs. The race happens when one CPU (say CPU 0) is disposing of an MSI while another CPU (say CPU 1) is setting up an MSI. CPU 0 calls (for example) pnv_teardown_msi_irqs(), which calls msi_bitmap_free_hwirqs() to indicate that the MSI (i.e. its hardware IRQ number) is no longer in use. Then, before CPU 0 gets to calling irq_dispose_mapping() to free up the virtal IRQ number, CPU 1 comes in and calls msi_bitmap_alloc_hwirqs() to allocate an MSI, and gets the same hardware IRQ number that CPU 0 just freed. CPU 1 then calls irq_create_mapping() to get a virtual IRQ number, which sees that there is currently a mapping for that hardware IRQ number and returns the corresponding virtual IRQ number (which is the same virtual IRQ number that CPU 0 was using). CPU 0 then calls irq_dispose_mapping() and frees that virtual IRQ number. Now, if another CPU comes along and calls irq_create_mapping(), it is likely to get the virtual IRQ number that was just freed, resulting in the same virtual IRQ number apparently being used for two different hardware interrupts. To fix this race, we just move the call to msi_bitmap_free_hwirqs() to after the call to irq_dispose_mapping(). Since virq_to_hw() doesn't work for the virtual IRQ number after irq_dispose_mapping() has been called, we need to call it before irq_dispose_mapping() and remember the result for the msi_bitmap_free_hwirqs() call. The pattern of calling msi_bitmap_free_hwirqs() before irq_dispose_mapping() appears in 5 places under arch/powerpc, and appears to have originated in commit05af7bd2d7
("[POWERPC] MPIC U3/U4 MSI backend") from 2007. Fixes:05af7bd2d7
("[POWERPC] MPIC U3/U4 MSI backend") Cc: stable@vger.kernel.org # v2.6.22+ Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
206 lines
5.2 KiB
C
206 lines
5.2 KiB
C
/*
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* Copyright 2006, Segher Boessenkool, IBM Corporation.
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* Copyright 2006-2007, Michael Ellerman, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2 of the
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* License.
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*
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*/
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <asm/mpic.h>
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#include <asm/prom.h>
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#include <asm/hw_irq.h>
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#include <asm/ppc-pci.h>
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#include <asm/msi_bitmap.h>
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#include "mpic.h"
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/* A bit ugly, can we get this from the pci_dev somehow? */
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static struct mpic *msi_mpic;
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static void mpic_u3msi_mask_irq(struct irq_data *data)
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{
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pci_msi_mask_irq(data);
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mpic_mask_irq(data);
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}
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static void mpic_u3msi_unmask_irq(struct irq_data *data)
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{
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mpic_unmask_irq(data);
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pci_msi_unmask_irq(data);
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}
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static struct irq_chip mpic_u3msi_chip = {
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.irq_shutdown = mpic_u3msi_mask_irq,
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.irq_mask = mpic_u3msi_mask_irq,
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.irq_unmask = mpic_u3msi_unmask_irq,
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.irq_eoi = mpic_end_irq,
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.irq_set_type = mpic_set_irq_type,
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.irq_set_affinity = mpic_set_affinity,
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.name = "MPIC-U3MSI",
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};
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static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos)
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{
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u8 flags;
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u32 tmp;
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u64 addr;
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pci_read_config_byte(pdev, pos + HT_MSI_FLAGS, &flags);
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if (flags & HT_MSI_FLAGS_FIXED)
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return HT_MSI_FIXED_ADDR;
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pci_read_config_dword(pdev, pos + HT_MSI_ADDR_LO, &tmp);
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addr = tmp & HT_MSI_ADDR_LO_MASK;
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pci_read_config_dword(pdev, pos + HT_MSI_ADDR_HI, &tmp);
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addr = addr | ((u64)tmp << 32);
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return addr;
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}
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static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
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{
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struct pci_bus *bus;
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unsigned int pos;
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for (bus = pdev->bus; bus && bus->self; bus = bus->parent) {
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pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING);
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if (pos)
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return read_ht_magic_addr(bus->self, pos);
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}
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return 0;
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}
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static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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/* U4 PCIe MSIs need to write to the special register in
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* the bridge that generates interrupts. There should be
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* theorically a register at 0xf8005000 where you just write
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* the MSI number and that triggers the right interrupt, but
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* unfortunately, this is busted in HW, the bridge endian swaps
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* the value and hits the wrong nibble in the register.
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*
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* So instead we use another register set which is used normally
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* for converting HT interrupts to MPIC interrupts, which decodes
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* the interrupt number as part of the low address bits
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*
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* This will not work if we ever use more than one legacy MSI in
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* a block but we never do. For one MSI or multiple MSI-X where
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* each interrupt address can be specified separately, it works
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* just fine.
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*/
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if (of_device_is_compatible(hose->dn, "u4-pcie") ||
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of_device_is_compatible(hose->dn, "U4-pcie"))
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return 0xf8004000 | (hwirq << 4);
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return 0;
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}
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static void u3msi_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct msi_desc *entry;
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irq_hw_number_t hwirq;
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for_each_pci_msi_entry(entry, pdev) {
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if (entry->irq == NO_IRQ)
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continue;
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hwirq = virq_to_hw(entry->irq);
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irq_set_msi_desc(entry->irq, NULL);
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irq_dispose_mapping(entry->irq);
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msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1);
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}
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return;
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}
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static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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unsigned int virq;
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struct msi_desc *entry;
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struct msi_msg msg;
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u64 addr;
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int hwirq;
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if (type == PCI_CAP_ID_MSIX)
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pr_debug("u3msi: MSI-X untested, trying anyway.\n");
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/* If we can't find a magic address then MSI ain't gonna work */
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if (find_ht_magic_addr(pdev, 0) == 0 &&
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find_u4_magic_addr(pdev, 0) == 0) {
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pr_debug("u3msi: no magic address found for %s\n",
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pci_name(pdev));
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return -ENXIO;
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}
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for_each_pci_msi_entry(entry, pdev) {
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hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1);
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if (hwirq < 0) {
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pr_debug("u3msi: failed allocating hwirq\n");
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return hwirq;
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}
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addr = find_ht_magic_addr(pdev, hwirq);
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if (addr == 0)
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addr = find_u4_magic_addr(pdev, hwirq);
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msg.address_lo = addr & 0xFFFFFFFF;
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msg.address_hi = addr >> 32;
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virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
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if (virq == NO_IRQ) {
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pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq);
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msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1);
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return -ENOSPC;
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}
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irq_set_msi_desc(virq, entry);
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irq_set_chip(virq, &mpic_u3msi_chip);
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irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
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pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
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virq, hwirq, (unsigned long)addr);
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printk("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
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virq, hwirq, (unsigned long)addr);
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msg.data = hwirq;
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pci_write_msi_msg(virq, &msg);
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hwirq++;
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}
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return 0;
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}
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int mpic_u3msi_init(struct mpic *mpic)
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{
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int rc;
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struct pci_controller *phb;
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rc = mpic_msi_init_allocator(mpic);
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if (rc) {
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pr_debug("u3msi: Error allocating bitmap!\n");
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return rc;
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}
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pr_debug("u3msi: Registering MPIC U3 MSI callbacks.\n");
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BUG_ON(msi_mpic);
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msi_mpic = mpic;
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list_for_each_entry(phb, &hose_list, list_node) {
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WARN_ON(phb->controller_ops.setup_msi_irqs);
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phb->controller_ops.setup_msi_irqs = u3msi_setup_msi_irqs;
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phb->controller_ops.teardown_msi_irqs = u3msi_teardown_msi_irqs;
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}
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return 0;
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}
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