mirror of
https://github.com/torvalds/linux
synced 2024-09-29 16:00:27 +00:00
b2d23158e6
Only copy the minimal definitions of instruction opcodes and formats in inst.h from arch/loongarch to tools/arch/loongarch, and also copy the definition of sign_extend64() to tools/include/linux/bitops.h to decode the following kinds of instructions: (1) stack pointer related instructions addi.d, ld.d, st.d, ldptr.d and stptr.d (2) branch and jump related instructions beq, bne, blt, bge, bltu, bgeu, beqz, bnez, bceqz, bcnez, b, bl and jirl (3) other instructions break, nop and ertn See more info about instructions in LoongArch Reference Manual: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Co-developed-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Jinyang He <hejinyang@loongson.cn> Co-developed-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
162 lines
3.1 KiB
C
162 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_INST_H
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#define _ASM_INST_H
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#include <linux/bitops.h>
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#define LOONGARCH_INSN_NOP 0x03400000
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enum reg0i15_op {
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break_op = 0x54,
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};
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enum reg0i26_op {
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b_op = 0x14,
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bl_op = 0x15,
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};
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enum reg1i21_op {
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beqz_op = 0x10,
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bnez_op = 0x11,
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bceqz_op = 0x12, /* bits[9:8] = 0x00 */
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bcnez_op = 0x12, /* bits[9:8] = 0x01 */
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};
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enum reg2_op {
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ertn_op = 0x1920e,
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};
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enum reg2i12_op {
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addid_op = 0x0b,
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andi_op = 0x0d,
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ldd_op = 0xa3,
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std_op = 0xa7,
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};
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enum reg2i14_op {
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ldptrd_op = 0x26,
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stptrd_op = 0x27,
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};
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enum reg2i16_op {
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jirl_op = 0x13,
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beq_op = 0x16,
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bne_op = 0x17,
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blt_op = 0x18,
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bge_op = 0x19,
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bltu_op = 0x1a,
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bgeu_op = 0x1b,
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};
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struct reg0i15_format {
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unsigned int immediate : 15;
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unsigned int opcode : 17;
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};
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struct reg0i26_format {
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unsigned int immediate_h : 10;
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unsigned int immediate_l : 16;
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unsigned int opcode : 6;
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};
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struct reg1i21_format {
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unsigned int immediate_h : 5;
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unsigned int rj : 5;
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unsigned int immediate_l : 16;
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unsigned int opcode : 6;
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};
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struct reg2_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int opcode : 22;
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};
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struct reg2i12_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 12;
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unsigned int opcode : 10;
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};
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struct reg2i14_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 14;
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unsigned int opcode : 8;
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};
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struct reg2i16_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 16;
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unsigned int opcode : 6;
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};
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union loongarch_instruction {
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unsigned int word;
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struct reg0i15_format reg0i15_format;
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struct reg0i26_format reg0i26_format;
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struct reg1i21_format reg1i21_format;
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struct reg2_format reg2_format;
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struct reg2i12_format reg2i12_format;
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struct reg2i14_format reg2i14_format;
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struct reg2i16_format reg2i16_format;
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};
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#define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
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enum loongarch_gpr {
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LOONGARCH_GPR_ZERO = 0,
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LOONGARCH_GPR_RA = 1,
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LOONGARCH_GPR_TP = 2,
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LOONGARCH_GPR_SP = 3,
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LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */
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LOONGARCH_GPR_A1, /* Reused as V1 for return value */
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LOONGARCH_GPR_A2,
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LOONGARCH_GPR_A3,
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LOONGARCH_GPR_A4,
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LOONGARCH_GPR_A5,
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LOONGARCH_GPR_A6,
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LOONGARCH_GPR_A7,
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LOONGARCH_GPR_T0 = 12,
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LOONGARCH_GPR_T1,
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LOONGARCH_GPR_T2,
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LOONGARCH_GPR_T3,
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LOONGARCH_GPR_T4,
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LOONGARCH_GPR_T5,
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LOONGARCH_GPR_T6,
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LOONGARCH_GPR_T7,
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LOONGARCH_GPR_T8,
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LOONGARCH_GPR_FP = 22,
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LOONGARCH_GPR_S0 = 23,
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LOONGARCH_GPR_S1,
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LOONGARCH_GPR_S2,
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LOONGARCH_GPR_S3,
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LOONGARCH_GPR_S4,
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LOONGARCH_GPR_S5,
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LOONGARCH_GPR_S6,
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LOONGARCH_GPR_S7,
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LOONGARCH_GPR_S8,
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LOONGARCH_GPR_MAX
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};
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#define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rj, \
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enum loongarch_gpr rd, \
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int offset) \
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{ \
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insn->reg2i16_format.opcode = OP; \
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insn->reg2i16_format.immediate = offset; \
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insn->reg2i16_format.rj = rj; \
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insn->reg2i16_format.rd = rd; \
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}
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DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op)
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#endif /* _ASM_INST_H */
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