Tomeu Vizoso b9e742c316 clk: tegra: Make clock initialization more robust ... Don't abort clock initialization if we cannot match an entry in tegra_clk_init_table to a valid entry in the clk array. Also log a corresponding error message. This was discovered when testing a patch that removed the EMC clock from tegra124_clks but left a mention in tegra_clk_init_table. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>		2014-09-18 14:56:53 +03:00
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clk-audio-sync.c
clk-divider.c	clk: tegra: use max divider if divider overflows	2014-02-17 16:18:34 +02:00
clk-id.h	clk: tegra: Fix xusb_hs_src clock hierarchy	2014-05-22 22:14:52 -07:00
clk-periph-gate.c	ARM: tegra: Move includes to include/soc/tegra	2014-07-17 13:26:47 +02:00
clk-periph.c	clk: tegra: Staticize tegra_clk_periph_no_gate_ops	2014-02-23 14:46:05 -08:00
clk-pll-out.c
clk-pll.c	clk: tegra: Use XUSB-compatible SATA PLL sequence	2014-07-08 11:29:55 +03:00
clk-super.c
clk-tegra-audio.c
clk-tegra-fixed.c
clk-tegra-periph.c	clk: tegra: fix vi_sensor clocks on Tegra124	2014-06-25 18:40:07 +03:00
clk-tegra-pmc.c
clk-tegra-super-gen4.c	clk: tegra: cclk_lp has a pllx/2 divider	2014-02-17 16:18:28 +02:00
clk-tegra20.c
clk-tegra30.c	ARM: tegra: Convert PMC to a driver	2014-07-17 14:58:43 +02:00
clk-tegra114.c	clk: tegra: fix vi_sensor clocks on Tegra124	2014-06-25 18:40:07 +03:00
clk-tegra124.c	clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks	2014-09-18 13:57:12 +03:00
clk.c	clk: tegra: Make clock initialization more robust	2014-09-18 14:56:53 +03:00
clk.h
Makefile