linux/arch/arm/mach-shmobile/headsmp-scu.S
Arnd Bergmann b8d56b61af Second Round of Renesas ARM Based SoC Cleanup for v4.6
* Remove stale comment from Kconfig
 * Consolidate SCU mapping code
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Merge tag 'renesas-cleanup2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup

Merge "Second Round of Renesas ARM Based SoC Cleanup for v4.6" from Simon Horman:

* Remove stale comment from Kconfig
* Consolidate SCU mapping code

* tag 'renesas-cleanup2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: Kconfig: Get rid of old comment
  ARM: shmobile: Consolidate SCU mapping code
2016-02-26 22:37:32 +01:00

41 lines
1.2 KiB
ArmAsm

/*
* Shared SCU setup for mach-shmobile
*
* Copyright (C) 2012 Bastian Hecht
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/memory.h>
/*
* Boot code for secondary CPUs.
*
* First we turn on L1 cache coherency for our CPU. Then we jump to
* secondary_startup that invalidates the cache and hands over control
* to the common ARM startup code.
*/
ENTRY(shmobile_boot_scu)
@ r0 = SCU base address
mrc p15, 0, r1, c0, c0, 5 @ read MPIDR
and r1, r1, #3 @ mask out cpu ID
lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
ldr r2, [r0, #8] @ SCU Power Status Register
mov r3, #3
lsl r3, r3, r1
bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
str r2, [r0, #8] @ write back
b secondary_startup
ENDPROC(shmobile_boot_scu)