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6c4b88ca59
Those wrapper drivers which use DMA define the REAL_DMA macro and those which use pseudo DMA define PSEUDO_DMA. These macros need to be removed for a number of reasons, not least of which is to have drivers share more code. Redefine the PDMA send and receive hooks as DMA setup hooks, so that the DMA code can be shared by all 5380 wrapper drivers. This will help to reunify the forked core driver. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Reviewed-by: Hannes Reinecke <hare@suse.com> Tested-by: Michael Schmitz <schmitzmic@gmail.com> Tested-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
97 lines
2.9 KiB
C
97 lines
2.9 KiB
C
/*
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* Trantor T128/T128F/T228 defines
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* Note : architecturally, the T100 and T128 are different and won't work
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*
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* Copyright 1993, Drew Eckhardt
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* Visionary Computing
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* (Unix and Linux consulting and custom programming)
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* drew@colorado.edu
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* +1 (303) 440-4894
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*
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* For more information, please consult
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*
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* Trantor Systems, Ltd.
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* T128/T128F/T228 SCSI Host Adapter
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* Hardware Specifications
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*
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* Trantor Systems, Ltd.
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* 5415 Randall Place
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* Fremont, CA 94538
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* 1+ (415) 770-1400, FAX 1+ (415) 770-9910
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*/
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#ifndef T128_H
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#define T128_H
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/*
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* The trantor boards are memory mapped. They use an NCR5380 or
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* equivalent (my sample board had part second sourced from ZILOG).
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* NCR's recommended "Pseudo-DMA" architecture is used, where
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* a PAL drives the DMA signals on the 5380 allowing fast, blind
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* transfers with proper handshaking.
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*/
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/*
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* Note : a boot switch is provided for the purpose of informing the
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* firmware to boot or not boot from attached SCSI devices. So, I imagine
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* there are fewer people who've yanked the ROM like they do on the Seagate
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* to make bootup faster, and I'll probably use this for autodetection.
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*/
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#define T_ROM_OFFSET 0
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/*
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* Note : my sample board *WAS NOT* populated with the SRAM, so this
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* can't be used for autodetection without a ROM present.
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*/
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#define T_RAM_OFFSET 0x1800
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/*
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* All of the registers are allocated 32 bytes of address space, except
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* for the data register (read/write to/from the 5380 in pseudo-DMA mode)
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*/
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#define T_CONTROL_REG_OFFSET 0x1c00 /* rw */
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#define T_CR_INT 0x10 /* Enable interrupts */
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#define T_CR_CT 0x02 /* Reset watchdog timer */
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#define T_STATUS_REG_OFFSET 0x1c20 /* ro */
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#define T_ST_BOOT 0x80 /* Boot switch */
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#define T_ST_S3 0x40 /* User settable switches, */
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#define T_ST_S2 0x20 /* read 0 when switch is on, 1 off */
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#define T_ST_S1 0x10
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#define T_ST_PS2 0x08 /* Set for Microchannel 228 */
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#define T_ST_RDY 0x04 /* 5380 DRQ */
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#define T_ST_TIM 0x02 /* indicates 40us watchdog timer fired */
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#define T_ST_ZERO 0x01 /* Always zero */
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#define T_5380_OFFSET 0x1d00 /* 8 registers here, see NCR5380.h */
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#define T_DATA_REG_OFFSET 0x1e00 /* rw 512 bytes long */
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#define NCR5380_implementation_fields \
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void __iomem *base
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#define T128_address(reg) \
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(((struct NCR5380_hostdata *)shost_priv(instance))->base + T_5380_OFFSET + ((reg) * 0x20))
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#define NCR5380_read(reg) readb(T128_address(reg))
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#define NCR5380_write(reg, value) writeb((value),(T128_address(reg)))
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
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#define NCR5380_dma_recv_setup t128_pread
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#define NCR5380_dma_send_setup t128_pwrite
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#define NCR5380_intr t128_intr
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#define NCR5380_queue_command t128_queue_command
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#define NCR5380_abort t128_abort
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#define NCR5380_bus_reset t128_bus_reset
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#define NCR5380_info t128_info
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#define NCR5380_io_delay(x) udelay(x)
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/* 15 14 12 10 7 5 3
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1101 0100 1010 1000 */
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#define T128_IRQS 0xc4a8
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#endif /* T128_H */
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