mirror of
https://github.com/torvalds/linux
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a173c390d9
SPE is part of the v8.2 architecture, so move its system register and field definitions into sysreg.h and the new PSB barrier into barrier.h Finally, move KVM over to using the generic definitions so that it doesn't have to open-code its own versions. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
127 lines
3.3 KiB
C
127 lines
3.3 KiB
C
/*
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* Based on arch/arm/include/asm/barrier.h
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*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#ifndef __ASSEMBLY__
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#define __nops(n) ".rept " #n "\nnop\n.endr\n"
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#define nops(n) asm volatile(__nops(n))
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#define sev() asm volatile("sev" : : : "memory")
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#define wfe() asm volatile("wfe" : : : "memory")
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#define wfi() asm volatile("wfi" : : : "memory")
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#define isb() asm volatile("isb" : : : "memory")
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#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
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#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
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#define psb_csync() asm volatile("hint #17" : : : "memory")
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#define mb() dsb(sy)
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#define rmb() dsb(ld)
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#define wmb() dsb(st)
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#define dma_rmb() dmb(oshld)
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#define dma_wmb() dmb(oshst)
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#define __smp_mb() dmb(ish)
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#define __smp_rmb() dmb(ishld)
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#define __smp_wmb() dmb(ishst)
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#define __smp_store_release(p, v) \
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do { \
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union { typeof(*p) __val; char __c[1]; } __u = \
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{ .__val = (__force typeof(*p)) (v) }; \
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compiletime_assert_atomic_type(*p); \
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switch (sizeof(*p)) { \
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case 1: \
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asm volatile ("stlrb %w1, %0" \
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: "=Q" (*p) \
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: "r" (*(__u8 *)__u.__c) \
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: "memory"); \
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break; \
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case 2: \
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asm volatile ("stlrh %w1, %0" \
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: "=Q" (*p) \
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: "r" (*(__u16 *)__u.__c) \
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: "memory"); \
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break; \
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case 4: \
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asm volatile ("stlr %w1, %0" \
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: "=Q" (*p) \
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: "r" (*(__u32 *)__u.__c) \
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: "memory"); \
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break; \
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case 8: \
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asm volatile ("stlr %1, %0" \
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: "=Q" (*p) \
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: "r" (*(__u64 *)__u.__c) \
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: "memory"); \
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break; \
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} \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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union { typeof(*p) __val; char __c[1]; } __u; \
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compiletime_assert_atomic_type(*p); \
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switch (sizeof(*p)) { \
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case 1: \
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asm volatile ("ldarb %w0, %1" \
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: "=r" (*(__u8 *)__u.__c) \
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: "Q" (*p) : "memory"); \
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break; \
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case 2: \
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asm volatile ("ldarh %w0, %1" \
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: "=r" (*(__u16 *)__u.__c) \
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: "Q" (*p) : "memory"); \
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break; \
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case 4: \
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asm volatile ("ldar %w0, %1" \
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: "=r" (*(__u32 *)__u.__c) \
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: "Q" (*p) : "memory"); \
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break; \
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case 8: \
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asm volatile ("ldar %0, %1" \
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: "=r" (*(__u64 *)__u.__c) \
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: "Q" (*p) : "memory"); \
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break; \
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} \
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__u.__val; \
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})
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#define smp_cond_load_acquire(ptr, cond_expr) \
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({ \
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typeof(ptr) __PTR = (ptr); \
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typeof(*ptr) VAL; \
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for (;;) { \
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VAL = smp_load_acquire(__PTR); \
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if (cond_expr) \
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break; \
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__cmpwait_relaxed(__PTR, VAL); \
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} \
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VAL; \
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})
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#include <asm-generic/barrier.h>
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_BARRIER_H */
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