linux/arch/c6x/platforms
Mark Salter 25b48ff852 C6X: fix timer64 initialization
Some SoCs have a timer block enable controlled through the DSCR registers.
There is a problem in the timer64 driver initialization where the code
accesses a timer register to get the divisor used to calculate timer clock
rate. If the timer block has not been enabled when this register read takes
place, an exception is generated. This patch makes sure that the timer block
is enabled before accessing the registers.

Signed-off-by: Mark Salter <msalter@redhat.com>
2012-01-08 15:12:17 -05:00
..
cache.c C6X: cache control 2011-10-06 19:48:10 -04:00
dscr.c C6X: DSCR - Device State Configuration Registers 2011-10-06 19:48:36 -04:00
emif.c C6X: fix layout of EMIFA registers 2012-01-08 15:12:09 -05:00
Kconfig C6X: build infrastructure 2011-10-06 19:47:25 -04:00
Makefile C6X: build infrastructure 2011-10-06 19:47:25 -04:00
megamod-pic.c C6X: interrupt handling 2011-10-06 19:47:54 -04:00
platform.c C6X: devicetree support 2011-10-06 19:47:33 -04:00
pll.c C6X: clocks 2011-10-06 19:48:07 -04:00
plldata.c C6X: clocks 2011-10-06 19:48:07 -04:00
timer64.c C6X: fix timer64 initialization 2012-01-08 15:12:17 -05:00