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https://github.com/torvalds/linux
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10ad34bc76
The multi-threading facility is introduced with the z13 processor family. This patch adds code to detect the multi-threading facility. With the facility enabled each core will surface multiple hardware threads to the system. Each hardware threads looks like a normal CPU to the operating system with all its registers and properties. The SCLP interface reports the SMT topology indirectly via the maximum thread id. Each reported CPU in the result of a read-scp-information is a core representing a number of hardware threads. To reflect the reduced CPU capacity if two hardware threads run on a single core the MT utilization counter set is used to normalize the raw cputime obtained by the CPU timer deltas. This scaled cputime is reported via the taskstats interface. The normal /proc/stat numbers are based on the raw cputime and are not affected by the normalization. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
207 lines
4.2 KiB
ArmAsm
207 lines
4.2 KiB
ArmAsm
/*
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* arch/s390/kernel/base.S
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*
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* Copyright IBM Corp. 2006, 2007
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* Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
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* Michael Holzheu <holzheu@de.ibm.com>
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/ptrace.h>
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#include <asm/sigp.h>
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#ifdef CONFIG_64BIT
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ENTRY(s390_base_mcck_handler)
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basr %r13,0
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0: lg %r15,__LC_PANIC_STACK # load panic stack
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aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_mcck_handler_fn
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lg %r1,0(%r1)
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ltgr %r1,%r1
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jz 1f
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basr %r14,%r1
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1: la %r1,4095
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lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
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lpswe __LC_MCK_OLD_PSW
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.section .bss
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.align 8
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.globl s390_base_mcck_handler_fn
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s390_base_mcck_handler_fn:
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.quad 0
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.previous
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ENTRY(s390_base_ext_handler)
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stmg %r0,%r15,__LC_SAVE_AREA_ASYNC
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basr %r13,0
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0: aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_ext_handler_fn
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lg %r1,0(%r1)
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ltgr %r1,%r1
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jz 1f
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basr %r14,%r1
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1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC
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ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
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lpswe __LC_EXT_OLD_PSW
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.section .bss
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.align 8
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.globl s390_base_ext_handler_fn
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s390_base_ext_handler_fn:
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.quad 0
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.previous
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ENTRY(s390_base_pgm_handler)
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stmg %r0,%r15,__LC_SAVE_AREA_SYNC
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basr %r13,0
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0: aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_pgm_handler_fn
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lg %r1,0(%r1)
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ltgr %r1,%r1
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jz 1f
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basr %r14,%r1
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lmg %r0,%r15,__LC_SAVE_AREA_SYNC
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lpswe __LC_PGM_OLD_PSW
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1: lpswe disabled_wait_psw-0b(%r13)
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.align 8
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disabled_wait_psw:
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.quad 0x0002000180000000,0x0000000000000000 + s390_base_pgm_handler
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.section .bss
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.align 8
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.globl s390_base_pgm_handler_fn
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s390_base_pgm_handler_fn:
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.quad 0
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.previous
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#
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# Calls diag 308 subcode 1 and continues execution
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#
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# The following conditions must be ensured before calling this function:
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# * Prefix register = 0
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# * Lowcore protection is disabled
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#
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ENTRY(diag308_reset)
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larl %r4,.Lctlregs # Save control registers
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stctg %c0,%c15,0(%r4)
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larl %r4,.Lfpctl # Floating point control register
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stfpc 0(%r4)
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larl %r4,.Lcontinue_psw # Save PSW flags
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epsw %r2,%r3
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stm %r2,%r3,0(%r4)
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larl %r4,.Lrestart_psw # Setup restart PSW at absolute 0
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lghi %r3,0
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lg %r4,0(%r4) # Save PSW
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sturg %r4,%r3 # Use sturg, because of large pages
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lghi %r1,1
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lghi %r0,0
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diag %r0,%r1,0x308
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.Lrestart_part2:
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lhi %r0,0 # Load r0 with zero
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lhi %r1,2 # Use mode 2 = ESAME (dump)
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sigp %r1,%r0,SIGP_SET_ARCHITECTURE # Switch to ESAME mode
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sam64 # Switch to 64 bit addressing mode
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larl %r4,.Lctlregs # Restore control registers
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lctlg %c0,%c15,0(%r4)
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larl %r4,.Lfpctl # Restore floating point ctl register
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lfpc 0(%r4)
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larl %r4,.Lcontinue_psw # Restore PSW flags
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lpswe 0(%r4)
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.Lcontinue:
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br %r14
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.align 16
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.Lrestart_psw:
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.long 0x00080000,0x80000000 + .Lrestart_part2
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.section .data..nosave,"aw",@progbits
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.align 8
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.Lcontinue_psw:
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.quad 0,.Lcontinue
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.previous
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.section .bss
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.align 8
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.Lctlregs:
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.rept 16
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.quad 0
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.endr
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.Lfpctl:
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.long 0
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.previous
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#else /* CONFIG_64BIT */
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ENTRY(s390_base_mcck_handler)
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basr %r13,0
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0: l %r15,__LC_PANIC_STACK # load panic stack
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ahi %r15,-STACK_FRAME_OVERHEAD
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l %r1,2f-0b(%r13)
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l %r1,0(%r1)
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ltr %r1,%r1
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jz 1f
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basr %r14,%r1
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1: lm %r0,%r15,__LC_GPREGS_SAVE_AREA
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lpsw __LC_MCK_OLD_PSW
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2: .long s390_base_mcck_handler_fn
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.section .bss
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.align 4
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.globl s390_base_mcck_handler_fn
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s390_base_mcck_handler_fn:
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.long 0
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.previous
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ENTRY(s390_base_ext_handler)
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stm %r0,%r15,__LC_SAVE_AREA_ASYNC
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basr %r13,0
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0: ahi %r15,-STACK_FRAME_OVERHEAD
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l %r1,2f-0b(%r13)
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l %r1,0(%r1)
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ltr %r1,%r1
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jz 1f
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basr %r14,%r1
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1: lm %r0,%r15,__LC_SAVE_AREA_ASYNC
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ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
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lpsw __LC_EXT_OLD_PSW
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2: .long s390_base_ext_handler_fn
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.section .bss
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.align 4
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.globl s390_base_ext_handler_fn
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s390_base_ext_handler_fn:
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.long 0
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.previous
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ENTRY(s390_base_pgm_handler)
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stm %r0,%r15,__LC_SAVE_AREA_SYNC
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basr %r13,0
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0: ahi %r15,-STACK_FRAME_OVERHEAD
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l %r1,2f-0b(%r13)
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l %r1,0(%r1)
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ltr %r1,%r1
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jz 1f
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basr %r14,%r1
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lm %r0,%r15,__LC_SAVE_AREA_SYNC
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lpsw __LC_PGM_OLD_PSW
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1: lpsw disabled_wait_psw-0b(%r13)
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2: .long s390_base_pgm_handler_fn
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disabled_wait_psw:
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.align 8
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.long 0x000a0000,0x00000000 + s390_base_pgm_handler
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.section .bss
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.align 4
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.globl s390_base_pgm_handler_fn
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s390_base_pgm_handler_fn:
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.long 0
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.previous
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#endif /* CONFIG_64BIT */
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