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b445e26cbf
In particular, avoid membar instructions in the delay slot of a jmpl instruction. UltraSPARC-I, II, IIi, and IIe have a bug, documented in the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51 The long and short of it is that if the IMU unit misses on a branch or jmpl, and there is a store buffer synchronizing membar in the delay slot, the chip can stop fetching instructions. If interrupts are enabled or some other trap is enabled, the chip will unwedge itself, but performance will suffer. We already had a workaround for this bug in a few spots, but it's better to have the entire tree sanitized for this rule. Signed-off-by: David S. Miller <davem@davemloft.net>
143 lines
3 KiB
ArmAsm
143 lines
3 KiB
ArmAsm
/* $Id: VISsave.S,v 1.6 2002/02/09 19:49:30 davem Exp $
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* VISsave.S: Code for saving FPU register state for
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* VIS routines. One should not call this directly,
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* but use macros provided in <asm/visasm.h>.
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*
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <asm/asi.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/visasm.h>
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#include <asm/thread_info.h>
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.text
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.globl VISenter, VISenterhalf
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/* On entry: %o5=current FPRS value, %g7 is callers address */
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/* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
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/* Nothing special need be done here to handle pre-emption, this
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* FPU save/restore mechanism is already preemption safe.
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*/
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.align 32
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VISenter:
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ldub [%g6 + TI_FPDEPTH], %g1
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brnz,a,pn %g1, 1f
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cmp %g1, 1
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stb %g0, [%g6 + TI_FPSAVED]
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stx %fsr, [%g6 + TI_XFSR]
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9: jmpl %g7 + %g0, %g0
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nop
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1: bne,pn %icc, 2f
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srl %g1, 1, %g1
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vis1: ldub [%g6 + TI_FPSAVED], %g3
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stx %fsr, [%g6 + TI_XFSR]
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or %g3, %o5, %g3
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stb %g3, [%g6 + TI_FPSAVED]
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rd %gsr, %g3
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clr %g1
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ba,pt %xcc, 3f
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stx %g3, [%g6 + TI_GSR]
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2: add %g6, %g1, %g3
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cmp %o5, FPRS_DU
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be,pn %icc, 6f
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sll %g1, 3, %g1
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stb %o5, [%g3 + TI_FPSAVED]
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rd %gsr, %g2
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add %g6, %g1, %g3
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stx %g2, [%g3 + TI_GSR]
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add %g6, %g1, %g2
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stx %fsr, [%g2 + TI_XFSR]
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sll %g1, 5, %g1
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3: andcc %o5, FPRS_DL|FPRS_DU, %g0
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be,pn %icc, 9b
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add %g6, TI_FPREGS, %g2
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andcc %o5, FPRS_DL, %g0
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membar #StoreStore | #LoadStore
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be,pn %icc, 4f
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add %g6, TI_FPREGS+0x40, %g3
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stda %f0, [%g2 + %g1] ASI_BLK_P
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stda %f16, [%g3 + %g1] ASI_BLK_P
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andcc %o5, FPRS_DU, %g0
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be,pn %icc, 5f
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4: add %g1, 128, %g1
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stda %f32, [%g2 + %g1] ASI_BLK_P
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stda %f48, [%g3 + %g1] ASI_BLK_P
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5: membar #Sync
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ba,pt %xcc, 80f
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nop
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.align 32
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80: jmpl %g7 + %g0, %g0
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nop
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6: ldub [%g3 + TI_FPSAVED], %o5
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or %o5, FPRS_DU, %o5
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add %g6, TI_FPREGS+0x80, %g2
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stb %o5, [%g3 + TI_FPSAVED]
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sll %g1, 5, %g1
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add %g6, TI_FPREGS+0xc0, %g3
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wr %g0, FPRS_FEF, %fprs
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membar #StoreStore | #LoadStore
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stda %f32, [%g2 + %g1] ASI_BLK_P
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stda %f48, [%g3 + %g1] ASI_BLK_P
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membar #Sync
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ba,pt %xcc, 80f
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nop
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.align 32
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80: jmpl %g7 + %g0, %g0
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nop
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.align 32
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VISenterhalf:
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ldub [%g6 + TI_FPDEPTH], %g1
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brnz,a,pn %g1, 1f
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cmp %g1, 1
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stb %g0, [%g6 + TI_FPSAVED]
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stx %fsr, [%g6 + TI_XFSR]
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clr %o5
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jmpl %g7 + %g0, %g0
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wr %g0, FPRS_FEF, %fprs
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1: bne,pn %icc, 2f
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srl %g1, 1, %g1
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ba,pt %xcc, vis1
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sub %g7, 8, %g7
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2: addcc %g6, %g1, %g3
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sll %g1, 3, %g1
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andn %o5, FPRS_DU, %g2
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stb %g2, [%g3 + TI_FPSAVED]
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rd %gsr, %g2
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add %g6, %g1, %g3
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stx %g2, [%g3 + TI_GSR]
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add %g6, %g1, %g2
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stx %fsr, [%g2 + TI_XFSR]
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sll %g1, 5, %g1
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3: andcc %o5, FPRS_DL, %g0
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be,pn %icc, 4f
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add %g6, TI_FPREGS, %g2
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membar #StoreStore | #LoadStore
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add %g6, TI_FPREGS+0x40, %g3
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stda %f0, [%g2 + %g1] ASI_BLK_P
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stda %f16, [%g3 + %g1] ASI_BLK_P
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membar #Sync
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ba,pt %xcc, 4f
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nop
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.align 32
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4: and %o5, FPRS_DU, %o5
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jmpl %g7 + %g0, %g0
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wr %o5, FPRS_FEF, %fprs
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