linux/drivers/clk/mediatek
Ryder Lee d42925189b clk: mediatek: fix the PCIe MAC clock parent
The PCIe function doesn't work as the clock tree of MAC layer is wrong.
Hence fix the clock table.

Fixes: 3b5e748615 ("clk: mediatek: add clock support for MT7629 SoC")
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-05 12:30:30 -08:00
..
clk-apmixed.c clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS 2015-10-01 12:06:00 +08:00
clk-cpumux.c clk: mediatek: Drop __init from mtk_clk_register_cpumuxes() 2018-11-30 00:39:19 -08:00
clk-cpumux.h clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work 2017-06-19 19:02:43 -07:00
clk-gate.c clk: mediatek: Add MT2701 clock support 2016-11-08 15:59:49 -08:00
clk-gate.h clk: mediatek: Add MT2701 clock support 2016-11-08 15:59:49 -08:00
clk-mt2701-aud.c clk: mediatek: add audsys support for MT2701 2018-03-20 00:24:42 -07:00
clk-mt2701-bdp.c clk: mediatek: Add MT2701 clock support 2016-11-08 15:59:49 -08:00
clk-mt2701-eth.c clk: mediatek: add mt2701 ethernet reset 2017-04-21 19:20:33 -07:00
clk-mt2701-g3d.c clk: mediatek: add g3dsys support for MT2701 and MT7623 2018-05-15 15:21:36 -07:00
clk-mt2701-hif.c reset: mediatek: Add MT2701 reset driver 2016-11-08 15:59:51 -08:00
clk-mt2701-img.c clk: mediatek: Add MT2701 clock support 2016-11-08 15:59:49 -08:00
clk-mt2701-mm.c clk: mediatek: Add MT2701 clock support 2016-11-08 15:59:49 -08:00
clk-mt2701-vdec.c clk: mediatek: Add MT2701 clock support 2016-11-08 15:59:49 -08:00
clk-mt2701.c clk: mediatek: remove unused array audio_parents 2018-08-30 18:29:36 -07:00
clk-mt2712-bdp.c clk: mediatek: Add MT2712 clock support 2017-11-02 01:02:53 -07:00
clk-mt2712-img.c clk: mediatek: Add MT2712 clock support 2017-11-02 01:02:53 -07:00
clk-mt2712-jpgdec.c clk: mediatek: Add MT2712 clock support 2017-11-02 01:02:53 -07:00
clk-mt2712-mfg.c clk: mediatek: Add MT2712 clock support 2017-11-02 01:02:53 -07:00
clk-mt2712-mm.c clk: mediatek: Add MT2712 clock support 2017-11-02 01:02:53 -07:00
clk-mt2712-vdec.c clk: mediatek: Add MT2712 clock support 2017-11-02 01:02:53 -07:00
clk-mt2712-venc.c clk: mediatek: Add MT2712 clock support 2017-11-02 01:02:53 -07:00
clk-mt2712.c clk: mediatek: update clock driver of MT2712 2018-03-19 14:37:40 -07:00
clk-mt6797-img.c clk: mediatek: add clk support for MT6797 2017-04-19 09:20:21 -07:00
clk-mt6797-mm.c clk: mediatek: add clk support for MT6797 2017-04-19 09:20:21 -07:00
clk-mt6797-vdec.c clk: mediatek: add clk support for MT6797 2017-04-19 09:20:21 -07:00
clk-mt6797-venc.c clk: mediatek: add clk support for MT6797 2017-04-19 09:20:21 -07:00
clk-mt6797.c clk: mediatek: add clk support for MT6797 2017-04-19 09:20:21 -07:00
clk-mt7622-aud.c clk: mediatek: add devm_of_platform_populate() for MT7622 audsys 2018-03-20 00:24:33 -07:00
clk-mt7622-eth.c clk: mediatek: add clock support for MT7622 SoC 2017-11-02 01:10:12 -07:00
clk-mt7622-hif.c clk: mediatek: add clock support for MT7622 SoC 2017-11-02 01:10:12 -07:00
clk-mt7622.c clk: mediatek: Drop more __init markings for driver probe 2018-11-30 00:39:39 -08:00
clk-mt7629-eth.c clk: mediatek: add clock support for MT7629 SoC 2018-11-29 22:52:05 -08:00
clk-mt7629-hif.c clk: mediatek: add clock support for MT7629 SoC 2018-11-29 22:52:05 -08:00
clk-mt7629.c clk: mediatek: fix the PCIe MAC clock parent 2018-12-05 12:30:30 -08:00
clk-mt8135.c clk: mediatek: Properly include clk.h 2015-07-20 10:53:09 -07:00
clk-mt8173.c clk: mediatek: export cpu multiplexer clock for MT8173 SoCs 2017-06-19 19:02:44 -07:00
clk-mtk.c clk: Convert to using %pOF instead of full_name 2017-07-21 15:49:54 -07:00
clk-mtk.h clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built 2018-01-10 13:41:15 -08:00
clk-pll.c clk: mediatek: add the option for determining PLL source clock 2017-11-02 01:07:51 -07:00
Kconfig clk: mediatek: add clock support for MT7629 SoC 2018-11-29 22:52:05 -08:00
Makefile clk: mediatek: add clock support for MT7629 SoC 2018-11-29 22:52:05 -08:00
reset.c clk: Convert to using %pOF instead of full_name 2017-07-21 15:49:54 -07:00