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656ad58ef1
This patch adds an OPAL console backend to the powerpc boot wrapper so that decompression failures inside the wrapper can be reported to the user. This is important since it typically indicates data corruption in the firmware and other nasty things. Currently this only works when building a little endian kernel. When compiling a 64 bit BE kernel the wrapper is always build 32 bit to be compatible with some 32 bit firmwares. BE support will be added at a later date. Another limitation of this is that only the "raw" type of OPAL console is supported, however machines that provide a hvsi console also provide a raw console so this is not an issue in practice. Actually-written-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> [mpe: Move #ifdef __powerpc64__ to avoid warnings on 32-bit] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
82 lines
1.8 KiB
C
82 lines
1.8 KiB
C
#ifndef _PPC64_PPC_ASM_H
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#define _PPC64_PPC_ASM_H
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/*
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*
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* Definitions used by various bits of low-level assembly code on PowerPC.
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*
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* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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/* Condition Register Bit Fields */
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#define cr0 0
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#define cr1 1
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#define cr2 2
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#define cr3 3
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#define cr4 4
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#define cr5 5
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#define cr6 6
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#define cr7 7
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/* General Purpose Registers (GPRs) */
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#define r0 0
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#define r1 1
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#define r2 2
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#define r3 3
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#define r4 4
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#define r5 5
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#define r6 6
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#define r7 7
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#define r8 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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#define SPRN_TBRL 268
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#define SPRN_TBRU 269
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#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
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#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
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#define MSR_LE 0x0000000000000001
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#define FIXUP_ENDIAN \
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tdi 0, 0, 0x48; /* Reverse endian of b . + 8 */ \
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b $+36; /* Skip trampoline if endian is good */ \
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.long 0x05009f42; /* bcl 20,31,$+4 */ \
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.long 0xa602487d; /* mflr r10 */ \
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.long 0x1c004a39; /* addi r10,r10,28 */ \
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.long 0xa600607d; /* mfmsr r11 */ \
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.long 0x01006b69; /* xori r11,r11,1 */ \
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.long 0xa6035a7d; /* mtsrr0 r10 */ \
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.long 0xa6037b7d; /* mtsrr1 r11 */ \
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.long 0x2400004c /* rfid */
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#endif /* _PPC64_PPC_ASM_H */
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