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https://github.com/torvalds/linux
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7356420cd3
Only mx508 based board is mach-mx50_rdp and it has been marked as BROKEN for several releases. mx508 currently lacks clock support. In case someone needs to add mx508 support back, then the recommended approach is to use device tree. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
110 lines
2.2 KiB
C
110 lines
2.2 KiB
C
/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*
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* This file contains the CPU initialization code.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include "hardware.h"
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static int mx5_cpu_rev = -1;
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#define IIM_SREV 0x24
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static int get_mx51_srev(void)
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{
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void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
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u32 rev = readl(iim_base + IIM_SREV) & 0xff;
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switch (rev) {
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case 0x0:
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return IMX_CHIP_REVISION_2_0;
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case 0x10:
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return IMX_CHIP_REVISION_3_0;
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default:
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return IMX_CHIP_REVISION_UNKNOWN;
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}
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}
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/*
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* Returns:
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* the silicon revision of the cpu
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* -EINVAL - not a mx51
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*/
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int mx51_revision(void)
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{
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if (!cpu_is_mx51())
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return -EINVAL;
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if (mx5_cpu_rev == -1)
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mx5_cpu_rev = get_mx51_srev();
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return mx5_cpu_rev;
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}
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EXPORT_SYMBOL(mx51_revision);
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#ifdef CONFIG_NEON
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/*
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* All versions of the silicon before Rev. 3 have broken NEON implementations.
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* Dependent on link order - so the assumption is that vfp_init is called
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* before us.
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*/
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int __init mx51_neon_fixup(void)
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{
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if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
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(elf_hwcap & HWCAP_NEON)) {
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elf_hwcap &= ~HWCAP_NEON;
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pr_info("Turning off NEON support, detected broken NEON implementation\n");
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}
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return 0;
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}
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#endif
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static int get_mx53_srev(void)
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{
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void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
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u32 rev = readl(iim_base + IIM_SREV) & 0xff;
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switch (rev) {
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case 0x0:
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return IMX_CHIP_REVISION_1_0;
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case 0x2:
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return IMX_CHIP_REVISION_2_0;
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case 0x3:
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return IMX_CHIP_REVISION_2_1;
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default:
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return IMX_CHIP_REVISION_UNKNOWN;
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}
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}
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/*
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* Returns:
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* the silicon revision of the cpu
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* -EINVAL - not a mx53
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*/
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int mx53_revision(void)
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{
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if (!cpu_is_mx53())
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return -EINVAL;
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if (mx5_cpu_rev == -1)
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mx5_cpu_rev = get_mx53_srev();
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return mx5_cpu_rev;
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}
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EXPORT_SYMBOL(mx53_revision);
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