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3a6f08a370
MPIC allows the use of private interrupt for each CPUs. The 28th first interrupts are per-cpu. This patch adds support to use them. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
296 lines
7.3 KiB
C
296 lines
7.3 KiB
C
/*
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* Marvell Armada 370 and Armada XP SoC IRQ handling
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <asm/mach/arch.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include <asm/hardware/cache-l2x0.h>
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/* Interrupt Controller Registers Map */
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
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#define ARMADA_370_XP_INT_CONTROL (0x00)
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#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
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#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
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#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
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#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
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#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
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#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
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#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
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#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
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#define ACTIVE_DOORBELLS (8)
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static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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/*
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* In SMP mode:
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* For shared global interrupts, mask/unmask global enable bit
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* For CPU interrtups, mask/unmask the calling CPU's bit
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*/
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static void armada_370_xp_irq_mask(struct irq_data *d)
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{
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#ifdef CONFIG_SMP
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_SET_MASK_OFFS);
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#else
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writel(irqd_to_hwirq(d),
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per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
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#endif
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}
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static void armada_370_xp_irq_unmask(struct irq_data *d)
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{
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#ifdef CONFIG_SMP
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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#else
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writel(irqd_to_hwirq(d),
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per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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#endif
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}
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#ifdef CONFIG_SMP
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static int armada_xp_set_affinity(struct irq_data *d,
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const struct cpumask *mask_val, bool force)
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{
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unsigned long reg;
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unsigned long new_mask = 0;
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unsigned long online_mask = 0;
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unsigned long count = 0;
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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int cpu;
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for_each_cpu(cpu, mask_val) {
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new_mask |= 1 << cpu_logical_map(cpu);
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count++;
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}
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/*
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* Forbid mutlicore interrupt affinity
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* This is required since the MPIC HW doesn't limit
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* several CPUs from acknowledging the same interrupt.
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*/
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if (count > 1)
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return -EINVAL;
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for_each_cpu(cpu, cpu_online_mask)
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online_mask |= 1 << cpu_logical_map(cpu);
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raw_spin_lock(&irq_controller_lock);
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reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
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reg = (reg & (~online_mask)) | new_mask;
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writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
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raw_spin_unlock(&irq_controller_lock);
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return 0;
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}
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#endif
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static struct irq_chip armada_370_xp_irq_chip = {
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.name = "armada_370_xp_irq",
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.irq_mask = armada_370_xp_irq_mask,
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.irq_mask_ack = armada_370_xp_irq_mask,
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.irq_unmask = armada_370_xp_irq_unmask,
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#ifdef CONFIG_SMP
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.irq_set_affinity = armada_xp_set_affinity,
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#endif
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};
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static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
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unsigned int virq, irq_hw_number_t hw)
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{
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armada_370_xp_irq_mask(irq_get_irq_data(virq));
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writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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irq_set_status_flags(virq, IRQ_LEVEL);
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if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) {
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irq_set_percpu_devid(virq);
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irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
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handle_percpu_devid_irq);
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} else {
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irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
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handle_level_irq);
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}
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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#ifdef CONFIG_SMP
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void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
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{
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int cpu;
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unsigned long map = 0;
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/* Convert our logical CPU mask into a physical one. */
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for_each_cpu(cpu, mask)
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map |= 1 << cpu_logical_map(cpu);
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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dsb();
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/* submit softirq */
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writel((map << 8) | irq, main_int_base +
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ARMADA_370_XP_SW_TRIG_INT_OFFS);
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}
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void armada_xp_mpic_smp_cpu_init(void)
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{
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/* Clear pending IPIs */
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writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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/* Enable first 8 IPIs */
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writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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/* Unmask IPI interrupt */
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writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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#endif /* CONFIG_SMP */
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static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
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.map = armada_370_xp_mpic_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init armada_370_xp_mpic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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u32 control;
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main_int_base = of_iomap(node, 0);
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per_cpu_int_base = of_iomap(node, 1);
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BUG_ON(!main_int_base);
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BUG_ON(!per_cpu_int_base);
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control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
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armada_370_xp_mpic_domain =
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irq_domain_add_linear(node, (control >> 2) & 0x3ff,
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&armada_370_xp_mpic_irq_ops, NULL);
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if (!armada_370_xp_mpic_domain)
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panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
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irq_set_default_host(armada_370_xp_mpic_domain);
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#ifdef CONFIG_SMP
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armada_xp_mpic_smp_cpu_init();
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/*
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* Set the default affinity from all CPUs to the boot cpu.
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* This is required since the MPIC doesn't limit several CPUs
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* from acknowledging the same interrupt.
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*/
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cpumask_clear(irq_default_affinity);
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cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
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#endif
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return 0;
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}
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asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
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*regs)
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{
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u32 irqstat, irqnr;
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do {
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irqstat = readl_relaxed(per_cpu_int_base +
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ARMADA_370_XP_CPU_INTACK_OFFS);
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irqnr = irqstat & 0x3FF;
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if (irqnr > 1022)
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break;
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if (irqnr > 0) {
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irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
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irqnr);
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handle_IRQ(irqnr, regs);
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continue;
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}
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#ifdef CONFIG_SMP
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/* IPI Handling */
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if (irqnr == 0) {
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u32 ipimask, ipinr;
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ipimask = readl_relaxed(per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
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& 0xFF;
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writel(0x0, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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/* Handle all pending doorbells */
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for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) {
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if (ipimask & (0x1 << ipinr))
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handle_IPI(ipinr, regs);
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}
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continue;
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}
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#endif
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} while (1);
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}
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static const struct of_device_id mpic_of_match[] __initconst = {
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{.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
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{},
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};
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void __init armada_370_xp_init_irq(void)
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{
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of_irq_init(mpic_of_match);
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#ifdef CONFIG_CACHE_L2X0
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l2x0_of_init(0, ~0UL);
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#endif
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}
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