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9b81c0211c
When the masked interrupt handler clears MSR[EE] for an interrupt in the PACA_IRQ_MUST_HARD_MASK set, it does not set PACA_IRQ_HARD_DIS. This makes them get out of synch. With that taken into account, it's only low level irq manipulation (and interrupt entry before reconcile) where they can be out of synch. This makes the code less surprising. It also allows the IRQ replay code to rely on the IRQ_HARD_DIS value and not have to mtmsrd again in this case (e.g., for an external interrupt that has been masked). The bigger benefit might just be that there is not such an element of surprise in these two bits of state. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
108 lines
2.3 KiB
ArmAsm
108 lines
2.3 KiB
ArmAsm
/*
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* Copyright 2010 IBM Corp, Benjamin Herrenschmidt <benh@kernel.crashing.org>
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*
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* Generic idle routine for Book3E processors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <asm/reg.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ppc-opcode.h>
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#include <asm/processor.h>
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#include <asm/thread_info.h>
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#include <asm/epapr_hcalls.h>
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#include <asm/hw_irq.h>
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/* 64-bit version only for now */
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#ifdef CONFIG_PPC64
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.macro BOOK3E_IDLE name loop
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_GLOBAL(\name)
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/* Save LR for later */
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mflr r0
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std r0,16(r1)
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/* Hard disable interrupts */
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wrteei 0
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/* Now check if an interrupt came in while we were soft disabled
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* since we may otherwise lose it (doorbells etc...).
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*/
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lbz r3,PACAIRQHAPPENED(r13)
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cmpwi cr0,r3,0
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bne 2f
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/* Now we are going to mark ourselves as soft and hard enabled in
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* order to be able to take interrupts while asleep. We inform lockdep
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* of that. We don't actually turn interrupts on just yet tho.
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*/
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#ifdef CONFIG_TRACE_IRQFLAGS
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stdu r1,-128(r1)
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bl trace_hardirqs_on
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addi r1,r1,128
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#endif
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li r0,IRQS_ENABLED
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stb r0,PACAIRQSOFTMASK(r13)
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/* Interrupts will make use return to LR, so get something we want
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* in there
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*/
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bl 1f
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/* And return (interrupts are on) */
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ld r0,16(r1)
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mtlr r0
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blr
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1: /* Let's set the _TLF_NAPPING flag so interrupts make us return
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* to the right spot
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*/
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CURRENT_THREAD_INFO(r11, r1)
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ld r10,TI_LOCAL_FLAGS(r11)
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ori r10,r10,_TLF_NAPPING
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std r10,TI_LOCAL_FLAGS(r11)
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/* We can now re-enable hard interrupts and go to sleep */
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wrteei 1
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\loop
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2:
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lbz r10,PACAIRQHAPPENED(r13)
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ori r10,r10,PACA_IRQ_HARD_DIS
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stb r10,PACAIRQHAPPENED(r13)
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blr
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.endm
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.macro BOOK3E_IDLE_LOOP
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1:
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PPC_WAIT(0)
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b 1b
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.endm
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/* epapr_ev_idle_start below is patched with the proper hcall
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opcodes during kernel initialization */
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.macro EPAPR_EV_IDLE_LOOP
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idle_loop:
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LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE))
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.global epapr_ev_idle_start
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epapr_ev_idle_start:
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li r3, -1
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nop
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nop
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nop
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b idle_loop
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.endm
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BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP
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BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP
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#endif /* CONFIG_PPC64 */
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