linux/arch/mips/ralink/reset.c
Sergio Paracuellos 201ddc0577 mips: ralink: remove reset related code
A proper clock driver for ralink SoCs has been added. This driver is also
a reset provider for the SoC. Hence there is no need to have reset related
code in 'arch/mips/ralink' folder anymore. The only code that remains is
the one related with mips_reboot_setup where a PCI reset is performed.
We maintain this because I cannot test old ralink board with PCI to be
sure all works if we remove also this code.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21 14:50:23 +02:00

44 lines
878 B
C

// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
* Copyright (C) 2013 John Crispin <john@phrozen.org>
*/
#include <linux/pm.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <asm/reboot.h>
#include <asm/mach-ralink/ralink_regs.h>
/* Reset Control */
#define SYSC_REG_RESET_CTRL 0x034
#define RSTCTL_RESET_PCI BIT(26)
#define RSTCTL_RESET_SYSTEM BIT(0)
static void ralink_restart(char *command)
{
if (IS_ENABLED(CONFIG_PCI)) {
rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
mdelay(50);
}
local_irq_disable();
rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
unreachable();
}
static int __init mips_reboot_setup(void)
{
_machine_restart = ralink_restart;
return 0;
}
arch_initcall(mips_reboot_setup);